27.7.9 VREF Control
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | VREFCTRL |
| Offset: | 0x020 |
| Reset: | 0x00000002 |
| Property: | RW |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TSEN | LPHIB | LPSTDBY | |||||||
| Access | RW | RW | RW | ||||||
| Reset | 0 | 1 | 0 |
Bit 4 – TSEN Temperature Sensor Output Enable
| Value | Description |
|---|---|
| 0 | Temperature sensor output to ADC disabled |
| 1 | Temperature sensor output to ADC Enabled |
Bit 1 – LPHIB Bandgap and Regulators Low Power Hibernate Enable
| Value | Name | Description |
|---|---|---|
| 0x0 | FullPower | In hibernate mode, bandgap is set to nominal power mode. As a consequence, enabled regulator(s) are set to nominal power mode. |
| 0x1 | LowPower | In hibernate mode, bandgap is set to low power mode. As a consequence, enabled regulator(s) are set to low power mode. |
Bit 0 – LPSTDBY Bandgap and Regulators Low Power Standby Enable
| Value | Name | Description |
|---|---|---|
| 0x0 | FullPower | In standby mode, bandgap and enabled regulator(s) are set to nominal power mode. |
| 0x1 | LowPower | In standby mode, bandgap and enabled regulator(s) are set to low power mode. |