27.7.8 VREG Control
Note: During normal operation, all
voltage regulators that are in use must be left in the On state to allow for the
proper transition between different low-power/standby states.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | VREGCTRL |
| Offset: | 0x01C |
| Reset: | 0x00000004 |
| Property: | RW |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| BKUP_VLD | SRAM_VLD | AVREGSTDBY[3:0] | |||||||
| Access | RW | RW | RW | RW | RW | RW | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| AVREGEN[3:0] | |||||||||
| Access | RW | RW | RW | RW | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ULDOLEVEL[1:0] | ULDOSTDBY | ULDOEN | CPEN[3:0] | ||||||
| Access | RW | RW | RW | RW | RW | RW | RW | RW | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SCAPEN | LVHIB | LVSTDBY | OFFSTDBY | VREGOUT[1:0] | |||||
| Access | R/W | RW | RW | RW | RW | RW | |||
| Reset | 0 | 0 | 0 | 1 | 0 | 0 | |||
Bit 31 – BKUP_VLD Backup Domain Valid Status Bit
Note: Hardware Cleared by Reset and Power Management Unit Whenever Backup power
domain is lost. Software (SW) Set by Backup Domain Initialization Code in BOOT
ROM when completed.
| Value | Description |
|---|---|
| 0 | Backup “BKUP” Power Domain has encountered a power loss and contents are not valid.(DEFAULT) |
| 1 | Backup “BKUP” Power Domain has not encountered a power loss. Contents are valid. |
Bit 30 – SRAM_VLD SRAM VALID Status Bit
Note:
- Hardware Clear by Reset and Power Management Units whenever SRAM power domain is lost.
- Should be set by Users SW Code once valid data has been written into System SRAM when " MCRAMC.CTRLA.ENABLE = 0" after SRAM is initialized by user.
| Value | Description |
|---|---|
| 0 | SRAM has encountered a power loss and contents are not valid. (DEAFAULT) |
| 1 | SRAM has not encountered a power loss. |
Bits 27:24 – AVREGSTDBY[3:0] Additional Voltage Regulator Configuration
| Value | Name | Description |
|---|---|---|
| 0x0 | OFFINSTDBY | Regulator is OFF while in sleep mode equal or deeper than standby mode. It is OFF in hibernate and backup mode as well. |
| 0x1 | ONINSTDBY | Regulator is ON in Standby mode if AVREGEN bit is set. is OFF from Hibernate mode. It is OFF in backup mode as well. |
Bits 19:16 – AVREGEN[3:0] Additional Voltage Regulator Enable
| Value | Description |
|---|---|
| 0x0 | USB and PLL regulators disabled (Default) |
| 0x1 | USB and PLL Regulator Enabled |
Bits 15:14 – ULDOLEVEL[1:0] User LDO Voltage Level Selection
| Value | Name | Description |
|---|---|---|
| 0x0 | 1p2v | Vout = 1.2v |
| 0x1 | 1p5v | Vout = 1.5v |
| 0x2 | 1p8v | Vout = 1.8v |
| 0x3 | 2p5v | Vout = 2.5v |
Bit 13 – ULDOSTDBY User LDO Voltage Regulator Configuration
| Value | Name | Description |
|---|---|---|
| 0x0 | OFFINSTDBY | Regulator is OFF while in sleep mode equal or deeper than standby mode. It is OFF in hibernate and backup mode as well. |
| 0x1 | ONINSTDBY | Regulator is ON in Standby mode. is OFF from Hibernate mode. It is OFF in backup mode as well. |
Bit 12 – ULDOEN User LDO Voltage Regulator Enable
| Value | Description |
|---|---|
| 0x0 | User LDO is disabled |
| 0x1 | User LDO is enabled |
Bits 11:8 – CPEN[3:0] Charge Pump Enable and Auto-enable.
| Value | Description | Requirements |
|---|---|---|
| 0x0 | All charge pumps disabled. | AVDD ≥ 2.5v |
| 0x1 | Enable charge pump for I/O analog mux and Analog Comparator (AC) | AVDD < 2.5v |
| --- | Reserved | |
| 0x3 | Enable charge pumps for I/O, AC, ADC |
Note:
- When AVDD < 2.5v the corresponding appropriate CPEN must be enabled.
- User must have previously enabled the charge pump clocks defined in Configuration Register 5, FUCFG5.
Bit 7 – SCAPEN Super Capacitor Charging Enable
| Value | Description |
|---|---|
| 0 | |
| 1 |
Bit 5 – LVHIB Low Voltage Hibernate Enable
| Value | Name | Description |
|---|---|---|
| 0x0 | 1p2v | In Hibernate mode, VDDCORE_BU and VDDCORE_RAM are set to 1.2v. |
| 0x1 | 0p8v | In Hibernate mode, VDDCORE_BU and VDDCORE_RAM are set to 0.8v |
Bit 4 – LVSTDBY Low Voltage Standby Enable
| Value | Name | Description |
|---|---|---|
| 0x0 | 1p2v | In standby mode, VDDCORE_BU, VDDCORE_RAM, VDDCORE_SW and optionnaly VDDCOREUSB/PLL are set to 1.2v. |
| 0x1 | 0p8v | In standby mode, VDDCORE_BU, VDDCORE_RAM, VDDCORE_SW and optionnaly VDDCOREUSB/PLL are set to 0.8v. |
Bit 2 – OFFSTDBY Off in Standby Control for VREGSW[N-1]. Useful for Riverside only.
| Value | Name | Description |
|---|---|---|
| 0x0 | OFF | In standby mode, VREGSW1,2,3 are OFF |
| 0x1 | ON | In standby mode, VREGSW1,2,3 are ON |
Bits 1:0 – VREGOUT[1:0] VREG Output Control in RUN mode only. Enable by production fuse by CALSUPC.VREGOUTEN
| Value | Name | Description |
|---|---|---|
| 0x0 | 1p2v | In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 1.2v. |
| 0x1 | 1p0v | In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 1.0v. |
| 0x2 | 0p8v | In Active mode, VDDCORE_RAM, VDDCORE_BU, VDDCORE_SW and optionnaly VDDCORE_PLL USB are set to 0.8v. |