31.1.11.4 Row Write Sequence

The largest block of data that can be programmed by a single NVMOP command is a row. As shown in Flash Module Construction, a row is 1024 bytes of data. ADDR is the row aligned address where the Flash address starts programming the data. The controller ignores the sub-row address bits and ALWAYS starts programming at the beginning of a row.

A Row Write sequence comprises the following steps:

  1. Write the entire row of data to be programmed into system SRAM. The source address must be word aligned and secure/non-secure zone consistent with the transaction type.
  2. <Desired NVMOP> is Row Write.
  3. Follow the Start Sequencer from Start Sequencer.
  4. Wait for NVM Interrupt from Interrupts.
  5. Check the INTFLAG bits to ensure that the program sequence completed successfully, and then clear all bits in INTFLAG. See Errors and Flags regarding error flags.

A row of Flash can be programmed if its associated page is not write protection see Debug Access Level.

The data transferred from RAM is buffered within the FCW. The FCW fetches enough data words to calculating ECC for each programming operation in the row.

The FCW automates programming the data into the Flash using contiguous Single Write operations. The data is double buffered, such that each programming sequence of four programming operations may execute while the next data are read from the internal system SRAM.

Note:
  1. The base address held in the SRCADDR register is not changed during the Row Write sequence.
  2. The DATAn registers may be affected by the Row Write sequence and cannot be guaranteed to hold prior data.

Row Write and ECC

Since Row Write uses multiple Quad Writes to update a row, it has the same features and restrictions as Quad Write.

Note: All configuration data held in flash and read before user boot up must be programmed, by software, using Quad Write or it will generate an ECC error when read.