31.1.11.3 Quad Write Sequence

The Quad Write operation implements a Quad Double Word programming. The 4, 32-bit instruction/data words to be programmed must be written to DATAn, n = 0,1,…,3, before the programming sequence is initiated. The Flash instruction word at the location pointed to by ADDR is programmed. The program operation must be aligned to a Flash word address, so the lower 5 bits are ignored for Quad Write.

The Quad Write sequence typically comprises the following steps

  1. <Desired NVMOP> is Quad Write.
  2. Follow the Start Sequencer from Start Sequencer.
  3. Wait for NVM Interrupt from Interrupts.
  4. Check the INTFLAG bits to ensure that the program sequence completed successfully, and then clear all bits in INTFLAG. See Errors and Flags about error flags.
  5. Unlock the hardware write mutex by setting the LOCK bit to ‘0’ and the OWNER field to ‘00’ simultaneously to the MUTEX register.

A flash address can be written if its associated page write protection is not enabled, see Debug Accesss Level. The FCW writes whatever is in DATAn when commanded.

Quad Write Timing

Quad Write timing is dominated by setup (Tnvs + Tpgs), program time (Tprog) and recovery (Trcv) delays. Using the specs shown in Non-Volatile Memory Controller (NVM) Electrical Specifications, the total time to program one QWord/QDWord is roughly:

   Quad Write Time = Tnvs + Tpgs + 4*Tprog + Trcv + Trw

If Pre-Programming, the first step adds roughly:

   Quad Write Time = 4*Tpreprog + Tprepgh + Tprepgs

Quad Write asserts programming voltage throughout the sequence to avoid duplicating setup and recovery delays. Consequently, a Quad Write operation takes less time than 4 Word/DWord Program operations.

Quad Write and ECC

Note: All configuration data held in flash and read before user boot up must be programmed, by software, using Quad Write or it will generate an ECC error when read.