25.5.15 Receiver Data Register High Byte
This register contains the MSb of the data received by the USART receiver, as well as status bits reflecting the status of the received data frame. The USART receiver is double-buffered, and this register always holds the data and status bits for the oldest received frame. If only one frame of data and status bits is present in the receive buffer, this register contains that information.
The buffer shifts out the data when either RXDATAL or RXDATAH is read, depending on the configuration. The register which does not lead to data being shifted must be read first to be able to read both bytes before shifting.
When the Character Size (CHSIZE) bits in the Control D (USARTn.CTRLD) register is configured to 9-bit mode with low byte first, reading RXDATAH shifts the receive buffer. In all other configurations, reading RXDATAL shifts the buffer.
| Name: | RXDATAH |
| Offset: | 0x11 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BUFOVF | FERR | PERR | RXC | DATA[8] | |||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 5 – BUFOVF Buffer Overflow
This flag is set for any byte that has been overwritten due a buffer overflow. A buffer overflow occurs when the receive buffer is full, a new frame is waiting in the receive shift register, and another new frame is received.
This flag is not used in the SPI Host mode.
Bit 4 – FERR Frame Error
This flag indicates that the received frame did not meet the requirements
expected by the receiver. When the Protocol Converter is enabled by PROTCONV in
the Control G (USARTn.CTRLG) register, this flag indicates that the frame
corresponds to neither a ‘0’ nor a ‘1’. In
other mode, this flag indicates that the stop bit was not received at the
expected time.
This flag is not used in the SPI Host mode.
Bit 3 – PERR Parity Error
This flag is set if parity checking is enabled and the received data contains a parity error. For more details on how parity is calculated, refer to the Parity section.
Bit 2 – RXC Receive Complete
Bit 0 – DATA[8] Receiver Data Register
When using a 9-bit frame size, this bit holds the ninth bit (MSb) of the received data.
If the Frame Format (FORM) bit field in the Control C (USARTn.CTRLC) register is configured to LIN Client (LINCLIENT) mode, this bit indicates whether the received data are within the response space of a LIN frame. The bit is cleared if the received data are in the protected identifier field; otherwise, it is set.