25.5.3 Control C


Bit	7	6	5	4	3	2	1	0
		DORD	CPHA		SAMPR	FORM[2:0]
Access		R/W	R/W		R/W	R/W	R/W	R/W
Reset		0	0		0	0	0	0

Bit 6 – DORD Data Order

This bit indicates the data order when a character is shifted out from the Data register. Both the receiver and transmitter use the same setting. Changing the DORD (Data Order) bit takes effect immediately and will disrupt any communication for both the receiver and the transmitter, potentially corrupting data transfer.

Value	Description
0	LSb of the data frame is transmitted first
1	MSb of the data frame is transmitted first

Bit 5 – CPHA Clock Phase

This bit controls the phase of the interface clock. For more information, refer to the Clock Generation section. This setting only functions when the Communication mode (CMODE) in Control A (USARTn.CTRLA) is configured to SPIHOST.

Value	Description
0	Data are sampled on the leading (first) edge
1	Data are sampled on the trailing (last) edge

Bit 3 – SAMPR Sample Rate

This bit is used to set the transfer rate in asynchronous communication mode. For IrDA encoding and LIN frame formats, SAMPR must be set to ‘0’. In synchronous operation, SAMPR has no effect and must always be ‘0’. For more details, refer to the Double-Speed Operation section.

Value	Description
0	16x oversampling
1	8x oversampling (double-speed mode)

Bits 2:0 – FORM[2:0] Frame Format

This bit field defines the frame format. Configuring this a value other than NORMAL enables the transmitting, receiving or detecting special frames. Normal frames can be transmitted and received in all formats.

Value	Name	Description
0x00	NORMAL	Normal USART frame
0x01	AUTOBAUD	Auto-baud mode
0x02	-	Reserved
0x03	-	Reserved
0x04	LINHOST	LIN Host mode
0x05	LINCLIENT	LIN Client mode
0x06	-	Reserved
0x07	-	Reserved

Name:	CTRLC
Offset:	0x02
Reset:	0x00
Property:	-