2.5.1 Clock Dividers

The PolarFire family provides 24 programmable clock dividers at the center of the edge on four sides of the device. Libero SoC selects the appropriate clock divider based on the input clock source. The clock divider input can come from any of the following:

• CCCs
• I/Os
• On-chip oscillators
• FPGA fabric

The divider clock outputs drive the global clock network.

Clock dividers create divide-by-1, divide-by-2, divide-by-3.5, divide-by-4, or divide-by-5 clocks. The divide-by-3.5 and divide-by-5 modes do not generate 50% duty-cycle clock outputs.

Each divider has its own synchronous reset (SRST_N) from the fabric. Resetting the divider takes place on the next falling edge of the input clock after SRST_N is asserted. The dividers come out of reset on the first falling edge of the input clock after SRST_N is de-asserted.

Each divider has a bit-slip (BIT_SLIP) control signal. On the rising edge of the BIT_SLIP signal, one clock pulse is swallowed by the divider circuit. This function is used in various word alignment schemes needed for SGMII and video applications. When the BIT_SLIP signal arrives, it pushes one input clock cycle delay on the divided clock. Depending on the divide mode, bit-slip might happen on the rising edge or falling edge. And, it might happen on the 1st, 2nd, or 3rd divided clock.

The following figure shows an example of using the reset and bit-slip operation of the dividers. The divide-by-1 clock is not affected by the reset or bit-slip operation.

The following figure shows the clock divider inputs and outputs. The clock dividers are accessible using CLKDIV configurator. The values for the clock dividers are configurable using the Libero SoC and are programmed during the device programming.