2.4.2 Preferred Clock Inputs Connectivity in CCCs

Preferred clock inputs can be configured as reference clock or feedback clock to the PLLs and DLLs present in each CCC. The preferred clock inputs which are capable of driving CCCs have dedicated connections to clock inputs (reference clock or feedback clock) of PLLs and/or DLLs present in the CCCs. For information about the connectivity of preferred clock inputs to PLLs and DLLs present in a CCC, see the respective PolarFire FPGA Package Pin Assignment Tables, RT PolarFire FPGA Package Pin Assignment Tables, or PolarFire SoC FPGA Package Pin Assignment Tables.

Each CCC consists of two PLLs (labeled as PLL0 and PLL1) and two DLLs (labeled as DLL0 and DLL1). CCCs and their internal PLLs and DLLs are labeled according to their locations in the device. For example, the CCC located in the northeast corner is labeled as CCC_NE. Similarly, the PLLs and DLLs present in the CCC_NE are labeled as PLL0_NE, PLL1_NE, DLL0_NE, and DLL1_NE. Each PLL has two reference clock inputs—REF_CLK_0 and REF_CLK_1.

Important: For PolarFire family, some of the preferred clock inputs have connections to feedback clock input of the PLL/DLL present in the CCC. It is required to choose a preferred clock input, which has connection to the PLL reference clock input for clock frequency synthesis. For information about preferred clock inputs connectivity to PLLs/DLLs and global clock network, see the respective PolarFire FPGA Package Pin Assignment Tables, RT PolarFire FPGA Package Pin Assignment Tables, PolarFire SoC FPGA Package Pin Assignment Tables.

For example, in PolarFire FPGA, the package pin T9 of MPF300T-FCG1152 device has pin name as GPIO219PB4/CLKIN_W_3/CCC_SW_CLKIN_W_3. The T9 pin can be used as a preferred clock input, which can connect to global clock network or CCC_SW. In the CCC_SW, the T9 pin is connected to feedback clock inputs of PLLs and reference clock inputs of DLLs. Therefore, the PLL frequency synthesis cannot be performed on the external clock connected to T9 in the MPF300T-FCG1152 device.

As another example, in PolarFire SoC FPGA, the package pin J13 of MPFS250TS-FCG1152 device has pin name as GPIO9PB1/CLKIN_S_8/CCC_SE_CLKIN_S_8. The J13 pin can be used as a preferred clock input, which can connect to global clock network or CCC_SE. In the CCC_SE, the J13 pin is connected to reference clock inputs of PLLs.