36 Revision History

Revision E (April 2026)
  • Sections:
    • Updated High-Resolution PWM with Fine Edge Placement, Communication Interfaces, Referenced Sources, 2.6. External Oscillator Layout Guidance, 3.3. Data Space Addressing, 4.2. Data Address Space, 5.4. ECC Fault Injection, 6. Resets, 6.1.1. Key Resources, 10.1.1. Source and Destination, 14.1. Overview, 18. Inter-Integrated Circuit (I2C), 19. Parallel Master Port (PMP), 22.1. Time Base Generator, 29. Power-Saving Features, 29.5.1. Key Resources, 30.6. Brown-out Reset (BOR), 30.8. JTAG Interface and 30.9. In-Circuit Debugger.
  • Tables:
    • Updated Table 1. dsPIC33CK512MP608 Motor Control/Power Supply Families, Table 2. dsPIC33CK512MP608 Motor Control/Power Supply Families with No CAN FD, Table 6. Terminology Cross References, Table 1-1. Pinout I/O Descriptions, Table 7-1. Trap Vector Details, Table 7-2. Interrupt Vector Details, Table 8-4. Selectable Input Sources (Maps Input to Function), Table 9-2. Interrupt Vector Details, Table 13-1. ADC External Input Availability, Table 22-5. Synchronization Sources, Table 26-1. CBG Channel Availability, Table 30-3. Device IDs for the dsPIC33CK512MP608 Family, Table 33-4. Thermal Packaging Characteristics, Table 33-5. Operating Voltage Specifications, Table 33-28. High-Speed PWMx Module Timing Requirements, Table 33-38. ADC Module Specifications, Table 33-40. DACx Module Specifications, Table 34-4. Thermal Packaging Characteristics and Table 34-6. DC Characteristics: Operating Current (IDD),
    • Added Die Temperature Diode Specifications and Internal LPRC Accuracy, Quadrature Decoder Timing Requirements, QEI Index Pulse Timing Requirements and Voltage Regulator Specifications.
  • Figures:
    • Updated Figure 1. 48-Pin TQFP/VQFN, Figure 2. 64-Pin TQFP, QFN, Figure 3. 80-pin TQFP, Figure 30-2. Watchdog Timer Block Diagram,
    • Added QEA/QEB Input Characteristics and QEA/QEB Input Characteristics.
  • Registers:
    • Updated 3.5.12. Data Space Write Page Register, 5.7.12. ECC System Status Display Register High, 7.7.8. Interrupt Request Flags Register 7, 7.7.11. Interrupt Request Flags Register 10, 7.7.13. Interrupt Request Flags Register 12, 7.7.21. Interrupt Enable Register 7, 7.7.55. Interrupt Priority Register 28, 7.7.70. Interrupt Priority Register 48, 7.7.74. Interrupt Control Register 2, 7.7.75. Interrupt Control Register 3, 8.13.34. Peripheral Pin Select Input Register 37, 8.13.54. Peripheral Pin Select Output Register 10, 9.11.8. APLL Output Divider Register, 9.7.75. Interrupt Control Register 3, 10.2.3.6. DMA Channel n Interrupt Register, 11.2.1. CAN2 Control Register Low, 11.2.28. CAN2 FIFO User Address Register x High (x = 1 to 7), 11.2.38. CAN Nominal Bit Time Configuration Register High, 11.2.67. CAN Transmit Event FIFO Control Register Low, 11.2.74. CAN Transmit Queue Control Register Low, 11.2.76. CAN Transmit Queue Status Register, 11.2.79. CAN FIFO Control Register x Low (x = 1 to 7), 11.2.80. CAN FIFO Control Register x High (x = 1 to 7), 11.2.81. CAN FIFO Status Register x (x = 1 to 7), 11.2.82. CAN FIFO User Address Register x Low (x = 1 to 7), 11.2.83. CAN FIFO User Address Register x High (x = 1 to 7), 12.6.13. PWM Generator x Control Register High, 12.6.25. PWM Generator x PCI Register Low, 13.4.1. ADC Control Register 1 Low, 13.4.4. ADC Control Register 2 High, 13.4.13. ADC Interrupt Enable Register Low, 13.4.14. ADC Interrupt Enable Register High, 13.4.23. ADC Channel Trigger 0 Selection Register Low, 13.4.24. ADC Channel Trigger 0 Selection Register High, 13.4.25. ADC Channel Trigger 1 Selection Register Low, 13.4.26. ADC Channel Trigger 1 Selection Register High, 13.4.27. ADC Channel Trigger 2 Selection Register Low, 13.4.28. ADC Channel Trigger 2 Selection Register High, 13.4.29. ADC Channel Trigger 3 Selection Register Low, 13.4.30. ADC Channel Trigger 3 Selection Register High, 13.4.31. ADC Channel Trigger 4 Selection Register Low, 13.4.32. ADC Channel Trigger 4 Selection Register High, 13.4.33. ADC Channel Trigger 5 Selection Register Low, 13.4.34. ADC Channel Trigger 5 Selection Register High, 13.4.35. ADC Channel Trigger 6 Selection Register Low, 13.4.36. ADC Channel Trigger 6 Selection Register High, 13.4.47. ADC Control Register 5 High, 14.3.4. DACx Control Low Register, 15.1.1. QEIx Control Register, 15.1.7. Position x Counter Hold Register, 22.6.1. CCPx Control 1 Low Register, 22.6.3. CCPx Control 2 Low Register, 22.6.4. CCPx Control 2 High Register, 22.6.6. CCPx Control 3 High Register, 24.2.4. PTG Broadcast Trigger Enable Low Register, 27.1.2. Op Amp Control Register High, 29.6.2. Peripheral Module Disable 1 Register, 30.2.1. FSEC Configuration Register, 30.2.2. FBSLIM Configuration Register, 30.2.3. FSIGN Configuration Register, 30.2.4. FOSCSEL Configuration Register, 30.2.5. FOSC Configuration Register, 30.2.6. FWDT Configuration Register, 30.2.7. FPOR Configuration Register, 30.2.8. FICD Configuration Register, 30.2.9. FDMTIVTL Configuration Register, 30.2.10. FDMTIVTH Configuration Register, 30.2.11. FDMTCNTL Configuration Register, 30.2.12. FDMTCNTH Configuration Register, 30.2.13. FDMT Configuration Register, 30.2.14. FDEVOPT Configuration Register, 30.2.15. FALTREG Configuration Register, 30.2.16. FBTSEQ Configuration Register and 30.2.17. FBOOT Configuration Register.
    • Removed 8.13.71. Peripheral Pin Select Output Register 27 through 8.13.80. Peripheral Pin Select Output Register 36.

Adds minor text edits throughout document.

Revision D (April 2026)

  • Sections:
    • Updated “10.1.3 Trigger Source”, “10.2.2 DMA Registers”, “12.4 PWM4H/L Output on Peripheral Pin Select”, “13.1 ADC Features Overview”, “18.2 Setting Baud Rate When Operating as a Bus Host”, “18.3 Client Address Masking”, Product Identification System, 22. Capture/Compare/PWM/Timer Modules (SCCP) and Package Details
    • Added: 5.5.1 Activating Flash OTP by ICSP Write Inhibit.
  • Tables:
    • Updated Table 7-2. Interrupt Vector Details, Table 10-1. DMA Channel Trigger Sources, Table 33-5. Operating Voltage Specifications, Table 33-10. DC Characteristics: Watchdog Timer Delta Current (ΔIWDT), Table 33-26. Internal FRC Accuracy, Table 33-33. SPIx Client Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 0) Timing Requirements, Table 33-34. SPIx Client Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 0), Table 33-35. SPIx Client Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 0), Table 33-38. UARTx Module I/O Timing Requirements, Table 33-39. ADC Module Specifications, Table 33-42. DACx Module Specifications, Table 33-45. Operational Amplifier Specifications, Table 34-5. Operating Voltage Specifications, Table 34-6. DC Characteristics: Operating Current (IDD) (Run), Table 34-7. DC Characteristics: Idle Current (IIDLE), Table 34-9. DC Characteristics: Operating Current (IIDLE), Table 34-13. Watchdog Timer Delta Current (ΔIWDT) and Table 34-22. DACx Module Specifications.
  • Figures:
    • Updated Figure 7-2. dsPIC33CK512MP608 Alternate Interrupt Vector Table, Figure 11-1. CAN FD Module Block Diagram, Figure 13-1. ADC Module Block Diagram and Figure 22-3. Output Compare x Block Diagram.
  • Registers:
    • Updated 6.1.2 Reset Control Register, 7.7.3. Interrupt Request Flags Register 2, 7.7.8. Interrupt Request Flags Register 7, 7.7.9. Interrupt Request Flags Register 8, 7.7.12. Interrupt Request Flags Register 11, 7.7.14. Interrupt Enable Register 0, 7.7.15. Interrupt Enable Register 1, 7.7.21. Interrupt Enable Register 7, 7.7.22. Interrupt Enable Register 8, 7.7.24. Interrupt Enable Register 10, 7.7.30. Interrupt Priority Register 3, 7.7.57. Interrupt Priority Register 30, 8.2.2.1 Analog Select for PORTx Register, 8.2.2.2 Output Enable for PORTx Register, 8.12.27 Peripheral Pin Select Input Register 25, 9.11.5 PLL Output Divider Register, 9.11.8 APLL Output Divider Register, 12.6.13 PWM Generator x Control Register High, 10.2.3.3 DMA Low Address Limit Register, 10.2.3.4 DMA High Address Limit Register, 10.2.3.6 DMA Channel n Interrupt Register, 11.2.4 CAN2 Nominal Bit Time Configuration Register High, 11.2.19 CAN2 Transmit Queue Control Register Low, 11.2.84 CAN FIFO User Address Register x High, 11.2.32 CAN2 Filter Object Register x Low, 11.2.33 CAN2 Filter Object Register x High, 12.6.15 PWM Generator x I/O Control Register Low, 12.7.19. PWM Generator x PCI Register Low, 12.7.21. PWM Generator x PCI Register Low, 12.7.23. PWM Generator x PCI Register Low, 13.4.5 ADC Control Register 3 Low, 13.4.9 ADC Input Mode Control Register 0 Low, 13.4.10 ADC Input Mode Control Register 0 High, 13.4.11 ADC Input Mode Control Register 1 Low, 13.4.12 ADC Input Mode Control Register 1 High, 13.4.15 ADC Data Ready Status Register Low,13.4.16 ADC Data Ready Status Register High, 13.4.22 ADC Digital Filter x Control Register, 13.4.39 ADC Early Interrupt Enable Register Low, 13.4.40 ADC Early Interrupt Enable Register High, 13.4.41 ADC Early Interrupt Status Register Low, 13.4.42 ADC Early Interrupt Status Register High, 13.4.45 ADC Buffer x Register, Register 14.4.1 DAC Control 1 Low Register, 14.4.2 DAC Control 2 Low Register, 14.4.3 DAC Control 2 High Register, 14.4.4 DACx Control Low Register, 15.1.2 QEIx I/O Control Register, 15.1.7 Position 1 Counter Hold Register, 15.1.8 Velocity x Counter Register Low, 15.1.10 Velocity 1 Counter Hold Register High, 15.1.17 Index 1 Counter Hold Register High, 17.1.6 SPIx Buffer Register Low, 17.1.7 SPIx Buffer Register High, 17.1.8 SPIx Baud Rate Generator Register Low, 17.1.11 SPIx Underrun Data Register Low, 17.1.12 SPIx Underrun Data Register Low, 7.7.71 CPU STATUS Register, 7.7.72 Core Control Register, 18.5.5 I2Cx Client Mode Address Mask Register, 20.3.1 SENTx Control Register 1, 20.3.2 SENTx Control Register 2, 20.3.3 SENTx Control Register 3, 21.1.1 Timer1 Control Register, 21.1.3 Period Register 1, 22.6.4 CCPx Control 2 High Register, 22.6.5 CCPx Control 3 High Register, 22.6.6 CCPx Status Register, 22.6.9 CCPx Period Low Register, 22.6.10 CCPx Period High Register, 22.6.11 CCPx Primary Compare Register, 22.6.12 CCPx Secondary Compare Register, 26.1.2 Current Bias Generator 50 μA Current Source Control Low Register, 26.1.3 Current Bias Generator 50 μA Current Source Control High Register, 28.1.8 DMT Post-Configure Count Status Register Low, 28.1.9 DMT Post-Configure Count Status Register High, 28.1.10 DMT Post-Configure Interval Status Register Low, 28.1.11 DMT Post-Configure Interval Status Register High, 29.6.1 Peripheral Module Disable Control Register, 29.6.2 Peripheral Module Disable 1 Register, 29.6.7 Peripheral Module Disable 7 Register, 30.2.6. FWDT Configuration Register and 30.7.1 Watchdog Timer Control Register Low.
    • Added Error Trap Origination Address Register Low and Error Trap Origination Address Register High, ADC Channel Trigger 5 Selection Register High, ADC Channel Trigger 6 Selection Register Low and ADC Channel Trigger 6 Selection Register High.

Adds minor text edits throughout document.

Revision C (January 2022)

This revision incorporates the following updates:

  • Sections:
    • Updates “Advanced Analog Features”, “Peripheral Features”, “Functional Safety Readiness”, “13. High-Speed, 12-Bit Analog-to-Digital Converter”, “13.1 ADC Features Overview”, “13.2 Temperature Sensor”.
    • Adds “9.4.1 Primary Oscillator Pin Functionality”, “14.1 Overview”, “16. Universal Asynchronous Receiver Transmitter (UART)” and “Product Identification System”.
  • Registers:
    • Updates 7.7.4 Interrupt Request Flags Register 3, 7.7.5 Interrupt Request Flags Register 4, 7.7.8 Interrupt Request Flags Register 7, 7.7.10 Interrupt Request Flags Register 9, 7.7.12 Interrupt Request Flags Register 11, 7.7.17 Interrupt Enable Register 3, 7.7.18 Interrupt Enable Register 4, 7.7.74 Interrupt Control Register 2, 7.7.75 Interrupt Control Register 3, 9.11.4 FRC Oscillator Tuning Register, 12.6.9 Combinatorial PWM Logic Control Register C, 12.6.10 PWM Event Output Control Register E, 13.4.8 ADC Control Register 4 High, 13.4.23 ADC Channel Trigger 0 Selection Register Low through 13.4.33 ADC Channel Trigger 5 Selection Register Low, 14.4.4 DACx Control Low Register, 17.1.1 SPIx Control Register 1 Low, 22.6.4 CCPx Control 2 High Register, 22.6.6 CCPx Status Register, 23.1.1 CLCx Control Register Low and 28.1.1 Deadman Timer Control Register.
    • Adds 9.11.12 Reference Clock Trim High Register, 20.1.2 Timer1 Counter Register and 20.1.3 Period Register 1.
    • Corrects bit ranges for PWM Control registers and CAN Control/Status registers.
    • Updates address offsets for PTG registers.
  • Tables:
    • Updates Table 7-1, Table 7-2, Table 10-1, Table 8-4, Table 22-6, Table 31-2, Table 33-10 and Table 33-45.
    • Adds Table 33-42.
  • Figures:
    • Updates Figure 4-2, Figure 4-3 and Figure 14-1.

Adds minor text edits throughout document.

Revision B (July 2021)

This revision incorporates the following updates:

  • Sections:
    • Updates “Qualification Support”, Section 9.6 “Low-Power RC Oscillator”, Section 29.6 “Power-Saving Control Registers”, Section 29.6.1 “Peripheral Module Disable Control Register Low” and Section 30.5.1 “Voltage Regulator Control Register”.
  • Tables:
    • Updates Table 3, Table 4, Table 33-7, Table 33-8, Table 33-9, Table 33-10, Table 33-18, Table 33-20, Table 33-26, Table 33-39, Table 33-44, Table 34-2, Table 34-6, Table 34-7, Table 34-10, Table 34-12, Table 34-13, Table 34-18. Table 34-19 and Table 34-20.
    • Removes Table 33-40, Table 34-7, Table 34-8, Table 34-9, Table 34-11 and Table 34-21.
    • Adds Table 34-9.
    • Removed Table 34-10.
  • Figures:
    • Updates Figure 2.
  • Equations:
    • Updates Equation 18-1.

Revision A (June 2021)

This is the initial version of the document.