7.6.7 RMII Timing

This section specifies the RMII interface transmit and receive timing.

In this mode, a 50 MHz clock must be input on the REFCLKIN pin. Refer to the RMII Clock Source - 50 MHz Oscillator section for additional clock details.

Note: The CRSDV pin performs both carrier sense and data valid functions. CRSDV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. If the PHY has additional bits to be presented on RXD[1:0] following the initial negation of CRSDV, then the device will assert CRSDV on cycles of REFCLKIN which present the second di-bit of each nibble and negate CRSDV on cycles of REFCLKIN which present the first di‑bit of a nibble. For additional information, refer to the RMII specification.

Table 7-14. RMII Timing
Description	Symbol	Min	Max	Units	Additional Information
REFCLKIN period	t_clkp	20		ns	Note 1
REFCLKIN high time	t_clkh	t_clkp* 0.45	t_clkp* 0.55	ns	Note 1
REFCLKIN low time	t_clkl	t_clkp* 0.45	t_clkp* 0.55	ns	Notes 1, 2
RXD[1:0], RXER, CRSDV output valid from rising edge of REFCLKIN	t_oval		16	ns
RXD[1:0], RXER, CRSDV output invalid from rising edge of REFCLKIN	t_oinvld	3.0		ns
TXD[1:0], TXEN setup time to rising edge of REFCLKIN	t_su	4.0		ns
TXD[1:0], TXEN hold time after rising edge of REFCLKIN	t_ihold	1.5		ns
Note: Design parameter, not tested. 1.8V 50 MHz clock input on REFCLKIN

Note: Timing was designed for system load between 5 pF and 20 pF.

LAN8670/1/2

7.6.7 RMII Timing