3.3.4.2 CDIN, CDOUT, and CDIN_FDBK_SEL

Higher-level DSP functions are supported by cascading individual Math blocks in a row. The two data signals, CDIN[47:0] and CDOUT[47:0], provide the cascading capability with an input select (CDIN_FDBK_SEL). Table 3-3 lists the possible settings of CDIN_FDBK_SEL for propagating CDIN to the E input of the adder.

To cascade Math blocks, the CDOUT of one block must feed the CDIN of an adjacent block. The CDOUT-to-CDIN connection is hardwired between the blocks within a row. Two different rows can be cascaded using fabric routing between two rows. Extra pipeline registers might be required to compensate for the extra delays added due to the fabric routing, which increases the latency of the chain.

The ability to cascade Math blocks is useful in filter designs. For example, an FIR filter can be constructed by cascading inputs to arrange a series of input data samples and cascading outputs to arrange a series of partial output results. Since the general routing in the fabric is not used, the cascading ability provides a high-performance and low-power implementation of DSP filter functions. For more information, see Cascading Math Blocks.