26.8.2 CRC Control
Name: | CRCCTRL |
Offset: | 0x02 |
Reset: | 0x0000 |
Property: | PAC Write-Protection, Enable-Protected |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
CRCMODE[1:0] | CRCSRC[5:0] | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CRCPOLY[1:0] | CRCBEATSIZE[1:0] | ||||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bits 15:14 – CRCMODE[1:0] CRC Operating Mode
Value | Name | Description |
---|---|---|
0x0 | DEFAULT | Default operating mode |
0x1 | — | Reserved |
0x2 | CRCMON | Memory CRC monitor operating mode |
0x3 | CRCGEN | Memory CRC generation operating mode |
Bits 13:8 – CRCSRC[5:0] CRC Input Source
These bits select the input source for generating the CRC. The selected source is locked until either the CRC generation is completed or the CRC module is disabled. This means the CRCSRC cannot be modified when the CRC operation is ongoing. The lock is signaled by the CRCBUSY status bit. CRC generation complete is generated and signaled from the selected source when used with the DMA channel.
Value | Name | Description |
---|---|---|
0x00 | NOACT | No action |
0x01 | IO | I/O interface |
0x02 - 0x1F | — | Reserved |
0x20 | CH0 | DMA channel 0 |
0x21 | CH1 | DMA channel 1 |
0x22 | CH2 | DMA channel 2 |
0x23 | CH3 | DMA channel 3 |
0x24 | CH4 | DMA channel 4 |
0x25 | CH5 | DMA channel 5 |
0x26 | CH6 | DMA channel 6 |
0x27 | CH7 | DMA channel 7 |
0x28 | CH8 | DMA channel 8 |
0x29 | CH9 | DMA channel 9 |
0x2A | CH10 | DMA channel 10 |
0x2B | CH11 | DMA channel 11 |
0x2C | CH12 | DMA channel 12 |
0x2D | CH13 | DMA channel 13 |
0x2E | CH14 | DMA channel 14 |
0x2F | CH15 | DMA channel 15 |
Bits 3:2 – CRCPOLY[1:0] CRC Polynomial Type
These bits select the CRC polynomial type.
Value | Name | Description |
---|---|---|
0x0 | CRC16 | CRC-16 (CRC-CCITT) |
0x1 | CRC32 | CRC32 (IEEE 802.3) |
0x2-0x3 | — | Reserved |
Bits 1:0 – CRCBEATSIZE[1:0] CRC Beat Size
These bits define the size of the data transfer for each bus access when the CRC is used with I/O interface.
Value | Name | Description |
---|---|---|
0x0 | BYTE | 8-bit bus transfer |
0x1 | HWORD | 16-bit bus transfer |
0x2 | WORD | 32-bit bus transfer |
0x3 | — | Reserved |