26.8.2 CRC Control

Name: CRCCTRL
Offset: 0x02
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected

Bit 15141312111098 
 CRCMODE[1:0]CRCSRC[5:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
     CRCPOLY[1:0]CRCBEATSIZE[1:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 15:14 – CRCMODE[1:0] CRC Operating Mode

These bits define the block transfer mode.
ValueNameDescription
0x0DEFAULTDefault operating mode
0x1Reserved
0x2CRCMONMemory CRC monitor operating mode
0x3CRCGENMemory CRC generation operating mode

Bits 13:8 – CRCSRC[5:0] CRC Input Source

These bits select the input source for generating the CRC. The selected source is locked until either the CRC generation is completed or the CRC module is disabled. This means the CRCSRC cannot be modified when the CRC operation is ongoing. The lock is signaled by the CRCBUSY status bit. CRC generation complete is generated and signaled from the selected source when used with the DMA channel.

ValueNameDescription
0x00NOACTNo action
0x01IOI/O interface
0x02 - 0x1FReserved
0x20CH0DMA channel 0
0x21CH1DMA channel 1
0x22CH2DMA channel 2
0x23CH3DMA channel 3
0x24CH4DMA channel 4
0x25CH5DMA channel 5
0x26CH6DMA channel 6
0x27CH7DMA channel 7
0x28CH8DMA channel 8
0x29CH9DMA channel 9
0x2ACH10DMA channel 10
0x2BCH11DMA channel 11
0x2CCH12DMA channel 12
0x2DCH13DMA channel 13
0x2ECH14DMA channel 14
0x2FCH15DMA channel 15

Bits 3:2 – CRCPOLY[1:0] CRC Polynomial Type

These bits select the CRC polynomial type.

ValueNameDescription
0x0CRC16CRC-16 (CRC-CCITT)
0x1CRC32CRC32 (IEEE 802.3)
0x2-0x3Reserved

Bits 1:0 – CRCBEATSIZE[1:0] CRC Beat Size

These bits define the size of the data transfer for each bus access when the CRC is used with I/O interface.

ValueNameDescription
0x0BYTE8-bit bus transfer
0x1HWORD16-bit bus transfer
0x2WORD32-bit bus transfer
0x3Reserved