26.8.5 CRC Status
| Name: | CRCSTATUS |
| Offset: | 0x0C |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CRCERR | CRCZERO | CRCBUSY | |||||||
| Access | R | R | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bit 2 – CRCERR CRC Error
1’ when the memory CRC monitor detects data corruption.Bit 1 – CRCZERO CRC Zero
This bit is cleared when a new CRC source is selected.
This bit is set when the CRC generation is complete and the CRC Checksum is zero.
Bit 0 – CRCBUSY CRC Module Busy
When used with an I/O interface (CRCCTRL.CRCSRC=0x1):
- This bit is cleared by writing a ‘
1’ to it - This bit is set when the CRC Data Input (CRCDATAIN) register is written
- Writing a ‘
1’ to this bit will clear the CRC Module Busy bit - Writing a ‘
0’ to this bit has no effect
When used with a DMA channel (CRCCTRL.CRCSRC=0x20..,0x3F):
- This bit is cleared when the corresponding DMA channel is disabled
- This bit is set when the corresponding DMA channel is enabled
- Writing a ‘
1’ to this bit has no effect - Writing a ‘
0’ to this bit has no effect