26.8.12 Pending Channels

Name: PENDCH
Offset: 0x2C
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 PENDCHn[15:8] 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 PENDCHn[7:0] 
Access RRRRRRRR 
Reset 00000000 

Bits 15:0 – PENDCHn[15:0] Pending Channel n [n=0..15]

This bit is cleared when a trigger execution defined by channel trigger action settings for DMA channel n is started, when a bus error for DMA channel n is detected or when DMA channel n is disabled. For details on trigger action settings, refer to CHCTRLB.TRIGACT.

This bit is set when a transfer is pending on DMA channel n.