26.8.23 Channel Status
Name: | CHSTATUS |
Offset: | 0x4F + n*0x10 [n=0..15] |
Reset: | 0x00 |
Property: | - |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CRCERR | FERR | BUSY | PEND | ||||||
Access | R/W | R | R | R | |||||
Reset | 0 | 0 | 0 | 0 |
Bit 3 – CRCERR Channel CRC Error
1
’ to it, or by clearing the CRC Error bit in the INTPEND register
(INTPEND.CRCERR). See INTPEND in the DMAC Register Summary from Related
Links.Bit 2 – FERR Channel Fetch Error
This bit is cleared when a software resume command is executed.
This bit is set when an invalid descriptor is fetched.
Bit 1 – BUSY Channel Busy
This bit is cleared when the channel trigger action is completed, when a bus error is detected or when the channel is disabled.
This bit is set when the DMA channel starts a DMA transfer.
Bit 0 – PEND Channel Pending
This bit is cleared when the channel trigger action is started, when a bus error is detected or when the channel is disabled. For details on trigger action settings, see CHCTRLB in the DMAC Register Summary from Related Links.
This bit is set when a transfer is pending on the DMA channel, as soon as the transfer request is received.