26.8.11 Busy Channels

Name: BUSYCH
Offset: 0x28
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 BUSYCHn[15:8] 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 BUSYCHn[7:0] 
Access RRRRRRRR 
Reset 00000000 

Bits 15:0 – BUSYCHn[15:0] Busy Channel n [n=15..0]

This bit is cleared when the channel trigger action for DMA channel n is complete, when a bus error for DMA channel n is detected, or when DMA channel n is disabled.

This bit is set when DMA channel n starts a DMA transfer.