26.8.22 Channel Interrupt Flag Status and Clear

This flag is cleared by writing a ‘1’ to it.

This flag is set when a block transfer with suspend block action is completed, when a software suspend command is executed, when a suspend event is received or when an invalid descriptor is fetched by the DMA.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the Channel Suspend interrupt flag for the corresponding channel.

For details on available software commands, see CHCTRLB in the DMAC Register Summary from Related Links.

For details on available event input actions, see CHCTRLB in the DMAC Register Summary from Related Links.

For details on available block actions, see BTCTRL in the DMAC Register Summary (SRAM) from Related Links.

This flag is cleared by writing a ‘1’ to it.

This flag is set when a block transfer is completed and the corresponding interrupt block action is enabled.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the Transfer Complete interrupt flag for the corresponding channel.

This flag is cleared by writing a ‘1’ to it.

This flag is set when a bus error is detected during a beat transfer or when the DMAC fetches an invalid descriptor.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the Transfer Error interrupt flag for the corresponding channel.