41.8.1 Control A

Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized (ENABLE, SWRST)

Bit 3130292827262524 
   CPTEN5CPTEN4CPTEN3CPTEN2CPTEN1CPTEN0 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 2322212019181716 
 DMAOS        
Access R/W 
Reset 0 
Bit 15141312111098 
 MSYNCALOCKPRESCYNC[1:0]RUNSTDBYPRESCALER[2:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
  RESOLUTION[1:0]   ENABLESWRST 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 24, 25, 26, 27, 28, 29 – CPTEN Capture Channel x Enable

These bits are used to select the capture or compare operation on channel x.

Writing a ‘1’ to CPTENx enables capture on channel x.

Writing a ‘0’ to CPTENx disables capture on channel x.

Bit 23 – DMAOS DMA One-Shot Trigger Mode

This bit enables the DMA One-shot Trigger Mode.

Writing a ‘1’ to this bit generates a DMA trigger on the TCC cycle following a TCC_CTRLBSET_CMD_DMAOS command.

Writing a ‘0’ to this bit generates DMA triggers on each TCC cycle.

This bit is not synchronized.

Note: DMA One-Shot mode is not available in RAMP1/RAMP2C/RAMP2CS modes.
ValueDescription
0The TCC controls its own counter.
1The counter is controlled by its Host TCC.

Bit 15 – MSYNC Host Synchronization (only for TCC client instance)

This bit must be set if the TCC counting operation must be synchronized on its Host TCC.

This bit is not synchronized.

ValueDescription
0The TCC controls its own counter.
1The counter is controlled by its Host TCC.

Bit 14 – ALOCK Auto Lock

This bit is not synchronized.

ValueDescription
0The Lock Update bit in the Control B register (CTRLB.LUPD) is not affected by overflow/underflow and re-trigger events
1CTRLB.LUPD is set to ‘1’ on each overflow/underflow or re-trigger event.

Bits 13:12 – PRESCYNC[1:0] Prescaler and Counter Synchronization

These bits select if, on re-trigger event, the Counter is cleared or reloaded on either the next GCLK_TCCx clock or on the next prescaled GCLK_TCCx clock. It is also possible to reset the prescaler on the re-trigger event.

These bits are not synchronized.

ValueNameDescription
Counter ReloadedPrescaler
0x0GCLKReload or reset Counter on next GCLK
0x1PRESCReload or reset Counter on next prescaler clock
0x2RESYNCReload or reset Counter on next GCLKReset prescaler counter
0x3Reserved

Bit 11 – RUNSTDBY Run in Standby

This bit is used to keep the TCC running in Standby mode.

This bit is not synchronized.

ValueDescription
0The TCC is halted in Standby mode.
1The TCC continues to run in Standby mode.

Bits 10:8 – PRESCALER[2:0] Prescaler

These bits select the Counter prescaler factor.

These bits are not synchronized.

ValueNameDescription
0x0DIV1Prescaler: GCLK_TCC
0x1DIV2Prescaler: GCLK_TCC/2
0x2DIV4Prescaler: GCLK_TCC/4
0x3DIV8Prescaler: GCLK_TCC/8
0x4DIV16Prescaler: GCLK_TCC/16
0x5DIV64Prescaler: GCLK_TCC/64
0x6DIV256Prescaler: GCLK_TCC/256
0x7DIV1024Prescaler: GCLK_TCC/1024

Bits 6:5 – RESOLUTION[1:0] Dithering Resolution

These bits increase the TCC resolution by enabling the dithering options.

These bits are not synchronized.

Table 41-9. Dithering
ValueNameDescription
0x0NONEThe dithering is disabled.
0x1DITH4Dithering is done every 16 PWM frames.

PER[3:0] and CCx[3:0] contain dithering pattern selection.

0x2DITH5Dithering is done every 32 PWM frames.

PER[4:0] and CCx[4:0] contain dithering pattern selection.

0x3DITH6Dithering is done every 64 PWM frames.

PER[5:0] and CCx[5:0] contain dithering pattern selection.

Bit 1 – ENABLE Enable

Due to synchronization, there is a delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE reads back immediately, and the ENABLE bit in the SYNCBUSY register (SYNCBUSY.ENABLE) is set. SYNCBUSY.ENABLE is cleared when the operation is complete.

ValueDescription
0The peripheral is disabled.
1The peripheral is enabled.

Bit 0 – SWRST Software Reset

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit resets all registers in the TCC (except DBGCTRL) to their initial state and the TCC is disabled.

Writing a ‘1’ to CTRLA.SWRST always takes precedence; all other writes in the same write-operation are discarded.

Due to synchronization, there is a delay from writing CTRLA.SWRST until the Reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the Reset is complete.

ValueDescription
0There is no Reset operation ongoing.
1The Reset operation is ongoing.