41.8.1 Control A
Name: | CTRLA |
Offset: | 0x00 |
Reset: | 0x00000000 |
Property: | PAC Write-Protection, Enable-Protected, Write-Synchronized (ENABLE, SWRST) |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
CPTEN5 | CPTEN4 | CPTEN3 | CPTEN2 | CPTEN1 | CPTEN0 | ||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
DMAOS | |||||||||
Access | R/W | ||||||||
Reset | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
MSYNC | ALOCK | PRESCYNC[1:0] | RUNSTDBY | PRESCALER[2:0] | |||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
RESOLUTION[1:0] | ENABLE | SWRST | |||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bits 24, 25, 26, 27, 28, 29 – CPTEN Capture Channel x Enable
These bits are used to select the capture or compare operation on channel x.
Writing a ‘1
’ to CPTENx enables capture on channel x.
Writing a ‘0
’ to CPTENx disables capture on channel x.
Bit 23 – DMAOS DMA One-Shot Trigger Mode
This bit enables the DMA One-shot Trigger Mode.
Writing a ‘1
’ to this bit generates a DMA trigger on the TCC cycle following a TCC_CTRLBSET_CMD_DMAOS command.
Writing a ‘0
’ to this bit generates DMA triggers on each TCC cycle.
This bit is not synchronized.
Value | Description |
---|---|
0 | The TCC controls its own counter. |
1 | The counter is controlled by its Host TCC. |
Bit 15 – MSYNC Host Synchronization (only for TCC client instance)
This bit must be set if the TCC counting operation must be synchronized on its Host TCC.
This bit is not synchronized.
Value | Description |
---|---|
0 | The TCC controls its own counter. |
1 | The counter is controlled by its Host TCC. |
Bit 14 – ALOCK Auto Lock
This bit is not synchronized.
Value | Description |
---|---|
0 | The Lock Update bit in the Control B register (CTRLB.LUPD) is not affected by overflow/underflow and re-trigger events |
1 | CTRLB.LUPD is set to ‘1 ’ on each overflow/underflow or re-trigger event. |
Bits 13:12 – PRESCYNC[1:0] Prescaler and Counter Synchronization
These bits select if, on re-trigger event, the Counter is cleared or reloaded on either the next GCLK_TCCx clock or on the next prescaled GCLK_TCCx clock. It is also possible to reset the prescaler on the re-trigger event.
These bits are not synchronized.
Value | Name | Description | |
---|---|---|---|
Counter Reloaded | Prescaler | ||
0x0 | GCLK | Reload or reset Counter on next GCLK | — |
0x1 | PRESC | Reload or reset Counter on next prescaler clock | — |
0x2 | RESYNC | Reload or reset Counter on next GCLK | Reset prescaler counter |
0x3 | Reserved | — | — |
Bit 11 – RUNSTDBY Run in Standby
This bit is used to keep the TCC running in Standby mode.
This bit is not synchronized.
Value | Description |
---|---|
0 | The TCC is halted in Standby mode. |
1 | The TCC continues to run in Standby mode. |
Bits 10:8 – PRESCALER[2:0] Prescaler
These bits select the Counter prescaler factor.
These bits are not synchronized.
Value | Name | Description |
---|---|---|
0x0 | DIV1 | Prescaler: GCLK_TCC |
0x1 | DIV2 | Prescaler: GCLK_TCC/2 |
0x2 | DIV4 | Prescaler: GCLK_TCC/4 |
0x3 | DIV8 | Prescaler: GCLK_TCC/8 |
0x4 | DIV16 | Prescaler: GCLK_TCC/16 |
0x5 | DIV64 | Prescaler: GCLK_TCC/64 |
0x6 | DIV256 | Prescaler: GCLK_TCC/256 |
0x7 | DIV1024 | Prescaler: GCLK_TCC/1024 |
Bits 6:5 – RESOLUTION[1:0] Dithering Resolution
These bits increase the TCC resolution by enabling the dithering options.
These bits are not synchronized.
Value | Name | Description |
---|---|---|
0x0 | NONE | The dithering is disabled. |
0x1 | DITH4 | Dithering is done every 16 PWM frames. PER[3:0] and CCx[3:0] contain dithering pattern selection. |
0x2 | DITH5 | Dithering is done every 32 PWM frames. PER[4:0] and CCx[4:0] contain dithering pattern selection. |
0x3 | DITH6 | Dithering is done every 64 PWM frames. PER[5:0] and CCx[5:0] contain dithering pattern selection. |
Bit 1 – ENABLE Enable
Due to synchronization, there is a delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE reads back immediately, and the ENABLE bit in the SYNCBUSY register (SYNCBUSY.ENABLE) is set. SYNCBUSY.ENABLE is cleared when the operation is complete.
Value | Description |
---|---|
0 | The peripheral is disabled. |
1 | The peripheral is enabled. |
Bit 0 – SWRST Software Reset
Writing a ‘0
’ to this bit has no effect.
Writing a ‘1
’ to this bit resets all registers in the TCC
(except DBGCTRL) to their initial state and the TCC is disabled.
Writing a ‘1
’ to CTRLA.SWRST always takes precedence; all
other writes in the same write-operation are discarded.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the Reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the Reset is complete.
Value | Description |
---|---|
0 | There is no Reset operation ongoing. |
1 | The Reset operation is ongoing. |