41.8.10 Interrupt Enable Clear
| Name: | INTENCLR |
| Offset: | 0x24 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| MC5 | MC4 | MC3 | MC2 | MC1 | MC0 | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FAULT1 | FAULT0 | FAULTB | FAULTA | DFS | UFS | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ERR | CNT | TRG | OVF | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bits 16, 17, 18, 19, 20, 21 – MCx Match or Capture Channel x Interrupt Disable [x=0..5]
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the corresponding Match or
Capture Channel x Interrupt Disable/Enable bit, which disables the Match or Capture
Channel x interrupt.
| Value | Description |
|---|---|
| 0 | The Match or Capture Channel x interrupt is disabled. |
| 1 | The Match or Capture Channel x interrupt is enabled. |
Bit 15 – FAULT1 Non-Recoverable Fault 1 Interrupt Disable
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the Non-Recoverable
Fault 1 Interrupt Disable/Enable bit, which disables the Non-Recoverable Fault 1
interrupt.
| Value | Description |
|---|---|
| 0 | The Non-Recoverable Fault 1 interrupt is disabled. |
| 1 | The Non-Recoverable Fault 1 interrupt is enabled. |
Bit 14 – FAULT0 Non-Recoverable Fault 0 Interrupt Disable
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the Non-Recoverable Fault 0
Interrupt Disable/Enable bit, which disables the Non-Recoverable Fault 0
interrupt.
| Value | Description |
|---|---|
| 0 | The Non-Recoverable Fault 0 interrupt is disabled. |
| 1 | The Non-Recoverable Fault 0 interrupt is enabled. |
Bit 13 – FAULTB Recoverable Fault B Interrupt Disable
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the Recoverable Fault
B Interrupt Disable/Enable bit, which disables the Recoverable Fault B interrupt.
| Value | Description |
|---|---|
| 0 | The Recoverable Fault B interrupt is disabled. |
| 1 | The Recoverable Fault B interrupt is enabled. |
Bit 12 – FAULTA Recoverable Fault A Interrupt Disable
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the Recoverable Fault A
Interrupt Disable/Enable bit, which disables the Recoverable Fault A interrupt.
| Value | Description |
|---|---|
| 0 | The Recoverable Fault A interrupt is disabled. |
| 1 | The Recoverable Fault A interrupt is enabled. |
Bit 11 – DFS Non-Recoverable Debug Fault State Interrupt Disable
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the Debug Fault State
Interrupt Disable/Enable bit, which disables the Debug Fault State interrupt.
| Value | Description |
|---|---|
| 0 | The Debug Fault State interrupt is disabled. |
| 1 | The Debug Fault State interrupt is enabled. |
Bit 10 – UFS Non-Recoverable Update Fault Interrupt Disable
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the Non-Recoverable Update
Fault Interrupt Disable/Enable bit, which disables the Non-Recoverable Update Fault
interrupt.
| Value | Description |
|---|---|
| 0 | The Non-Recoverable Update Fault interrupt is disabled. |
| 1 | The Non-Recoverable Update Fault interrupt is enabled. |
Bit 3 – ERR Error Interrupt Disable
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the Error Interrupt
Disable/Enable bit, which disables the Error interrupt.
| Value | Description |
|---|---|
| 0 | The Error interrupt is disabled. |
| 1 | The Error interrupt is enabled. |
Bit 2 – CNT Counter Interrupt Disable
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the Counter Interrupt
Disable/Enable bit, which disables the Counter interrupt.
| Value | Description |
|---|---|
| 0 | The Counter interrupt is disabled. |
| 1 | The Counter interrupt is enabled. |
Bit 1 – TRG Retrigger Interrupt Disable
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the Retrigger
Interrupt Disable/Enable bit, which disables the Retrigger interrupt.
| Value | Description |
|---|---|
| 0 | The Retrigger interrupt is disabled. |
| 1 | The Retrigger interrupt is enabled. |
Bit 0 – OVF Overflow Interrupt Disable
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the Overflow
Interrupt Disable/Enable bit, which disables the Overflow interrupt.
| Value | Description |
|---|---|
| 0 | The Overflow interrupt is disabled. |
| 1 | The Overflow interrupt is enabled. |