41.8.3 Control B Set
| Name: | CTRLBSET |
| Offset: | 0x05 |
| Reset: | 0x00 |
| Property: | PAC Write-Protection, Write-Synchronized, Read-Synchronized |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CMD[2:0] | IDXCMD[1:0] | ONESHOT | LUPD | DIR | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:5 – CMD[2:0] TCC Command
These bits can be used for software control of the re-triggering and stop commands of the TCC. When a command is executed, the CMD bit field will be read back as zero. The commands are executed on the next prescaled GCLK_TCCx clock cycle.
Writing a ‘0’ to this bit has no effect.
Writing a valid value to this bit group, as shown in the following table, will set the associated command.
| Value | Name | Description |
|---|---|---|
| 0x0 | NONE | No action |
| 0x1 | RETRIGGER | Force start, restart or retrigger |
| 0x2 | STOP | Force stop |
| 0x3 | UPDATE | Force update of double buffered registers |
| 0x4 | READSYNC | Force a read synchronization of COUNT |
| 0x5 | DMAOS | One-shot DMA trigger |
Bits 4:3 – IDXCMD[1:0] Ramp Index Command
These bits can be used to force cycle A and cycle B changes in the RAMP2 and RAMP2A operation. On the timer/counter update condition, the command is executed, the IDX flag in the STATUS register is updated and the IDXCMD command is cleared.
Writing a ‘0’ to this bit has no effect.
Writing a valid value to these bits will set a command.
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | Command disabled: IDX toggles between cycles A and B |
| 0x1 | SET | Set IDX: cycle B will be forced in the next cycle |
| 0x2 | CLEAR | Clear IDX: cycle A will be forced in next cycle |
| 0x3 | HOLD | Hold IDX: the next cycle will be the same as the current cycle. |
Bit 2 – ONESHOT One-Shot
This bit controls one-shot operation of the TCC. When in one-shot operation, the TCC will stop counting on the next overflow/underflow condition or a stop command.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will enable the one-shot operation.
| Value | Description |
|---|---|
| 0 | The TCC will count continuously. |
| 1 | The TCC will stop counting on the next underflow/overflow condition. |
Bit 1 – LUPD Lock Update
This bit controls the update operation of the TCC buffered registers.
When CTRLB.LUPD is set, the hardware UPDATE registers, with the value from their buffered registers, are disabled. Disabling the update ensures that all buffer registers are valid before a hardware update is performed. After all the buffer registers are loaded correctly, the buffered registers can be unlocked.
This bit has no effect when the input capture operation is enabled.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will disable the register's updates on the hardware UPDATE condition.
| Value | Description |
|---|---|
| 0 | The CCBx, PERB, PGVB and PGEB buffer registers values are copied into the corresponding CCx, PER, PGV and PGE registers on hardware update condition. |
| 1 | The CCBx, PERB, PGVB and PGEB buffer registers values are not copied into CCx, PER, PGV and PGE registers on hardware update condition. |
Bit 0 – DIR Counter Direction
This bit is used to change the direction of the counter.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will set the bit and make the counter count down.
| Value | Description |
|---|---|
| 0 | The timer/counter is counting up (incrementing). |
| 1 | The timer/counter is counting down (decrementing). |