41.8.14 Counter Value

Note: Prior to any read access, this register must be synchronized by the user writing the according TCC Command value to the Control B Set register (CTRLBSET.CMD = READSYNC).
Name: COUNT
Offset: 0x34
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
 COUNT[23:16] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 COUNT[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 COUNT[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 23:0 – COUNT[23:0] Counter Value

These bits hold the value of the Counter register.

Note:
  • When the TCC is configured as a 16-bit timer/counter, the excess bits are read ‘0’.
  • This bit field occupies the MSBs of the register, [23:m]. m is dependent on the Resolution bit in the Control A register (CTRLA.RESOLUTION):
    CTRLA.RESOLUTION Bits [23:m]
    0x0 - NONE 23:0 (depicted)
    0x1 - DITH4 23:4
    0x2 - DITH5 23:5
    0x3 - DITH6 23:6