41.8.12 Interrupt Flag Status and Clear

Name:	INTFLAG
Offset:	0x2C
Reset:	0x00000000
Property:	-


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
			MC5	MC4	MC3	MC2	MC1	MC0
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	FAULT1	FAULT0	FAULTB	FAULTA	DFS	UFS
Access	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
					ERR	CNT	TRG	OVF
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0

Bits 16, 17, 18, 19, 20, 21 – MCx Match or Capture Channel x Interrupt Flag [x=0..5]

This flag is set on the next CLK_TCC_COUNT cycle after a match with the compare condition or when the CCx register contains a valid capture value.

Writing a ‘0’ to one of these bits has no effect.

Writing a ‘1’ to one of these bits clears the corresponding Match or Capture Channel x interrupt flag.

In the Capture operation, this flag is automatically cleared when the CCx register is read.

Bit 15 – FAULT1 Non-Recoverable Fault 1 Interrupt Flag

This flag is set on the next CLK_TCC_COUNT cycle after a Non-Recoverable Fault 1 occurs.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the Non-Recoverable Fault 1 interrupt flag.

Bit 14 – FAULT0 Non-Recoverable Fault 0 Interrupt Flag

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the Non-Recoverable Fault 0 interrupt flag.

Bit 13 – FAULTB Recoverable Fault B Interrupt Flag

This flag is set on the next CLK_TCC_COUNT cycle after a Recoverable Fault B occurs.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the Recoverable Fault B interrupt flag.

Bit 12 – FAULTA Recoverable Fault A Interrupt Flag

This flag is set on the next CLK_TCC_COUNT cycle after a Recoverable Fault A occurs.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the Recoverable Fault A interrupt flag.

Bit 11 – DFS Non-Recoverable Debug Fault State Interrupt Flag

This flag is set on the next CLK_TCC_COUNT cycle after a Debug Fault State occurs.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the Debug Fault State interrupt flag.

Bit 10 – UFS Non-Recoverable Update Fault Interrupt Flag

This flag is set when the RAMP index changes and the Lock Update bit is set (CTRLBSET.LUPD).

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the Non-Recoverable Update Fault Interrupt Flag.

Bit 3 – ERR Error Interrupt Flag

This flag is set if a new capture occurs on a channel while the corresponding Match or Capture Channel x interrupt flag is one. In which case, there is no place to store the new capture.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the Error interrupt flag.

Bit 2 – CNT Counter Interrupt Flag

This flag is set on the next CLK_TCC_COUNT cycle after a counter event occurs.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the CNT interrupt flag.

Bit 1 – TRG Retrigger Interrupt Flag

This flag is set on the next CLK_TCC_COUNT cycle after a counter retrigger occurs.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the Retrigger interrupt flag.

Bit 0 – OVF Overflow Interrupt Flag

This flag is set on the next CLK_TCC_COUNT cycle after an overflow condition occurs.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the Overflow interrupt flag.

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