41.8.2 Control B Clear

The user can change this register without doing a read-modify-write operation. Changes in this register will, also, be reflected in the Control B Set (CTRLBSET) register.

Name:	CTRLBCLR
Offset:	0x04
Reset:	0x00
Property:	PAC Write-Protection, Write-Synchronized, Read-Synchronized


Bit	7	6	5	4	3	2	1	0
	CMD[2:0]			IDXCMD[1:0]		ONESHOT	LUPD	DIR
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:5 – CMD[2:0] TCC Command

These bits can be used for software control of re-triggering and stop commands of the TCC. When a command is executed, the CMD bit field reads back as ‘0’. The commands are executed on the next prescaled GCLK_TCCx clock cycle.

Writing a ‘0’ to this bit group has no effect.

Writing a ‘1’ to any of these bits clears the pending command.

Value	Name	Description
0x0	NONE	No action
0x1	RETRIGGER	Clear start, restart or retrigger
0x2	STOP	Force stop
0x3	UPDATE	Force update of double buffered registers
0x4	READSYNC	Force COUNT read synchronization
0x5	DMAOS	One-shot DMA trigger

Bits 4:3 – IDXCMD[1:0] Ramp Index Command

These bits can be used to force cycle A and cycle B changes in the RAMP2 and RAMP2A operation. On the timer/counter update condition, the command is executed, the IDX flag in STATUS register is updated and the IDXCMD command is cleared.

Writing a ‘0’ to these bits has no effect.

Writing a ‘1’ to any of these bits clears the pending command.

Value	Name	Description
0x0	DISABLE	DISABLE Command disabled: IDX toggles between cycles A and B
0x1	SET	Set IDX: cycle B will be forced in the next cycle
0x2	CLEAR	Clear IDX: cycle A will be forced in next cycle
0x3	HOLD	Hold IDX: the next cycle will be the same as the current cycle.

Bit 2 – ONESHOT One-Shot

This bit controls the one-shot operation of the TCC. When the one-shot operation is enabled, the TCC stops counting on the next overflow/underflow condition or on a stop command.

Writing a ‘0’ to this bit has no effect

Writing a ‘1’ to this bit disables the one-shot operation.

Value	Description
0	The TCC will update the counter value on overflow/underflow condition and continue operation.
1	The TCC will stop counting on the next underflow/overflow condition.

Bit 1 – LUPD Lock Update

This bit controls the update operation of the TCC buffered registers.

When CTRLB.LUPD is cleared, the hardware UPDATE registers, with the value from their buffered registers, are enabled.

This bit has no effect when the input capture operation is enabled.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit enables the registers updates on the hardware UPDATE condition.

Value	Description
0	The CCBx, PERB, PGVB and PGEB buffer registers values are copied into the corresponding CCx, PER, PGV and PGE registers on hardware update condition.
1	The CCBx, PERB, PGVB and PGEB buffer registers values are not copied into the corresponding CCx, PER, PGV and PGE registers on hardware update condition.

Bit 0 – DIR Counter Direction

This bit is used to change the direction of the counter.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit set the bit and makes the counter count down.

Value	Description
0	The timer/counter is counting up (incrementing).
1	The timer/counter is counting down (decrementing).