41.8.20 Period Buffer Value

Name: PERBUF
Offset: 0x6C
Reset: 0x00FFFFFF
Property: Write-Synchronized, Read-Synchronized

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
 PERBUF[17:10] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 
Bit 15141312111098 
 PERBUF[9:2] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 
Bit 76543210 
 PERBUF[1:0]DITHERBUF[5:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 

Bits 23:6 – PERBUF[17:0] Period Buffer Value

These bits hold the value of the Period Buffer register. The value is copied to the PER register on the UPDATE condition.

Note: When the TCC is configured as a 16-bit timer/counter, the excess bits are read as ‘0’.
Note: This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bits in the Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTIONBits [23:m]
0x0 - NONE23:0
0x1 - DITH423:4
0x2 - DITH523:5
0x3 - DITH623:6 (depicted)

Bits 5:0 – DITHERBUF[5:0] Dithering Buffer Cycle Number

These bits represent the PER.DITHER bits buffer. When the double buffering is enabled, the value of this bit field is copied to the PER.DITHER bits on an UPDATE condition.
Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTIONBits [n:0]
0x0 - NONE
0x1 - DITH43:0
0x2 - DITH54:0
0x3 - DITH65:0 (depicted)