1 Silicon Issue Summary
| Module | Item/Feature | Summary | Affected Silicon Revisions | ||
|---|---|---|---|---|---|
| A | B | C | |||
| ACC | ACC output connection issue | The Analog Comparator (ACC) output is not connected to the PWM event line. | X | ||
| ADC | SleepWalking | ADC SleepWalking is not functional. | X | ||
| ADC | Last channel trigger | Last channel trigger limitation | X | ||
| ADC | Trigger events | ADC trigger events RTCOUT0 and RTCOUT1 are not functional. | X | ||
| CLASSD | Differential Output mode | Unexpected offset and noise level in Differential Output mode | X | ||
| AUDIO PLL | Audio PLL output frequency range | Audio PLL output frequency range not compliant | X | ||
| FLEXCOM | FLEXCOM SMBUS alert | FLEXCOM SMBUS alert signaling is not functional | X | X | X |
| GMAC | Timestamps and PTP packets | Bad association of timestamps and PTP packets | X | X | X |
| GMAC | Screening registers not working | Screening registers (GMAC_ST1RPQx and GMAC_ST2RPQx) not working | X | X | X |
| HSIC | HSIC startup | At HSIC start-up, the strobe default state is wrong | X | ||
| I2SC | I2SC sent data | I2SC first sent data corrupted | X | X | X |
| MCAN(1) | CRC | Flexible data rate feature does not support CRC | X | X | X |
| MCAN(1) | MCAN_IR.MRAF interrupt | Needless activation of interrupt MCAN_IR.MRAF | X | X | X |
| MCAN(2) | Bus Integration state | Return of receiver from Bus Integration state after Protocol Exception Event | X | X | X |
| MCAN(2) | Message RAM/RAM Arbiter | Message RAM/RAM Arbiter not responding in time | X | X | X |
| MCAN(2) | Frame receiving | Data loss (payload) in case storage of a received frame has not completed until end of EOF field is reached | X | X | X |
| MCAN(1) | Edge filtering | Edge filtering causes mis-synchronization when falling edge at Rx input pin coincides with end of integration phase | X | X | X |
| MCAN(2) | MCAN_NBTP.NTSEG2 | Configuration of MCAN_NBTP.NTSEG2 = ’0’ not allowed | X | X | X |
| MCAN(2) | DAR mode | Retransmission in DAR mode due to lost arbitration at the first two identifier bits | X | X | X |
| MCAN(2) | Tx FIFO message | Tx FIFO message sequence inversion | X | X | X |
| MCAN(2) | HPM interrupt | Unexpected High Priority Message (HPM) interrupt | X | X | X |
| MCAN(2) | Transmitted message | Issue message transmitted with wrong arbitration and control fields | X | X | X |
| MCAN(2) | Debug message handling state machine not reset | Debug message handling state machine not reset to Idle state when CCCR.INIT is set | X | X | X |
| MCAN(1) | Frame transmitted despite cancellation | Frame transmitted despite confirmed transmit cancellation for CAN-FD messages with more than 8 data bytes | X | X | X |
| MPDDRC | tFAW timing | tFAW timing violation | X | ||
| PMC | GCLK fields | GCLK fields are reprogrammed unexpectedly | X | ||
| PMC | PMC SleepWalking | PMC SleepWalking is not functional | X | ||
| PMC | PMC_MCKR.PRES field | Change of the field PMC_MCKR.PRES is not allowed if Master/Processor Clock Prescaler frequency is too high | X | X | X |
| PTC | Wrong pull-up value on PD[18:3] during reset | Incorrect pull-up value | X | X | X |
| PWM | Fault Protection to Hi-Z for PWMx output | Fault Protection to Hi-Z for PWMx output is not functional | X | X | X |
| QSPI | DLYCS delay | QSPI hangs with long DLYCS | X | X | X |
| RTC | RTC_SR.TDERR flag | RTC_SR.TDERR flag is stuck at 0 | X | X | X |
| RTC | Truncated read access to RTC_TIMALR (UTC_MODE) | Read access truncated to the first 24 bits for register RTC_TIMALR (UTC_MODE) | X | X | X |
| ROM Code | Frequency support for SAM-BA Monitor | Main external clock frequency support for SAM-BA® Monitor limitation | X | ||
| ROM Code | Watchdog | Watchdog reset occurs when reenabling the watchdog | X | ||
| ROM Code | SPI frequency | SPI frequency at bootup is not 11 MHz | X | ||
| ROM Code | JTAG_TCK | JTAG_TCK on IOSET 4 pin has a wrong configuration after boot | X | X | X |
| ROM Code | SDMMC0 and SDMMC1 boot | The card detect pin is not correctly sampled in the ROM code | X | ||
| ROM Code | UART connection to SAM-BA Monitor |
UART blocks USB connection to SAM-BA Monitor | X | X | X |
| ROM Code | Secure Boot Mode: AES-RSA X.509 Certificate Serial Number Length Limit | The length of serial numbers is limited to 16 bytes by the ROM code. | X | X | X |
| SDMMC | Software 'Reset For all' command | Software 'Reset For all' command is not guaranteed | X | X | X |
| SDMMC | Status flag INTCLKS | Status flag INTCLKS may not work correctly | X | ||
| SDMMC | Sampling clock tuning procedure | Sampling clock tuning procedure may freeze | X | X | X |
| SDMMC | SDMMC I/O calibration does not work | The impedance calibration mechanism for the SDMMC I/Os does not work | X | X | X |
| SFC | Partial Fuse Masking | The Partial Fuse Masking function does not work | X | ||
| SFC | Fuse matrix first bits | The first two bits of each 32-bit block of the fuse matrix cannot be written | X | ||
| SFC | Fuse matrix programming | Fuse matrix programming requires a main clock (MAINCK) frequency between 10 and 15 MHz | X | X | X |
| SFC | Fuse matrix read | Fuse matrix read requires a main clock (MAINCK) frequency below 28 MHz | X | X | X |
| SFR | Serial number | The serial number stored in the SFR registers (SFR_SN0 and SFR_SN1) is not correct | X | ||
| SSC | TD output | Unexpected delay on TD output | X | X | X |
| TWIHS | Clear command | The TWI/TWIHS Clear command does not work | X | X | X |
| WDT | Restart command | Restart command of WDT may reset the DDR controller | X | X | X |
Note:
- This erratum is not relevant for CAN 2.0.
- This erratum is applicable for CAN 2.0.