36.5.28 SQI TAP CONTROL REGISTER
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | TAPCON |
| Offset: | 0x15C |
| Reset: | 0x0000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DDRCLKINDLY[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SDRDATINDLY[3:0] | DDRDATINDLY[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SDRCLKINDLY[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DATAOUTDLY[3:0] | CLKOUTDLY[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | RW | RW | RW | RW | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 29:24 – DDRCLKINDLY[5:0] SQI Clock Input Delay in DDR Mode bits <5:0>
These bits are used to add fractional delays to SQI Clock Input while sampling the incoming data in DDR mode.
| Value | Description |
|---|---|
| 111111 | 64 taps added on clock input |
| 111110 | 63 taps added on clock input |
| 000001 | 2 taps added on clock input |
| 000000 | 1 tap added on clock input |
Bits 23:20 – SDRDATINDLY[3:0] SQI Data Input Delay in SDR Mode bits <3:0>
These bits are used to add fractional delays to SQI Data Output while writing the data to the Flash in SDR mode.
| Value | Description |
|---|---|
| 1111 | 16 taps added on data input |
| 1110 | 15 taps added on data input |
| 0001 | 2 taps added on data input |
| 0000 | 1 tap added on data input |
Bits 19:16 – DDRDATINDLY[3:0] SQI Data Output Delay in DDR Mode bits <3:0>
These bits are used to add fractional delays to SQI Data Output while writing the data to the Flash in DDR mode.
| Value | Description |
|---|---|
| 1111 | 16 taps added on data input |
| 1110 | 15 taps added on data input |
| 0001 | 2 taps added on data input |
| 0000 | 1 tap added on data input |
Bits 13:8 – SDRCLKINDLY[5:0] SQI Clock Input Delay in SDR Mode bits <5:0>
These bits are used to add fractional delays to SQI Clock Input while sampling the incoming data in DDR mode.
| Value | Description |
|---|---|
| 111111 | 64 taps added on clock input |
| 111110 | 63 taps added on clock input |
| 000001 | 2 taps added on clock input |
| 000000 | 1 tap added on clock input |
Bits 7:4 – DATAOUTDLY[3:0] SQI Data Output Delay bits <3:0>
These bits are used to add fractional delays to SQI Data Output while writing the data to the Flash in all modes of operation.
| Value | Description |
|---|---|
| 1111 | 16 taps added on data output |
| 1110 | 15 taps added on data output |
| 0001 | 2 taps added on data output |
| 0000 | 1 tap added on data output |
Bits 3:0 – CLKOUTDLY[3:0] SQI Clock Output Delay bits <3:0>
These bits are used to add fractional delays to SQI Clock Output while writing the data to the Flash in all modes of operation.
| Value | Description |
|---|---|
| 1111 | 16 taps added on clock output |
| 1110 | 15 taps added on clock output |
| 0001 | 2 taps added on clock output |
| 0000 | 1 tap added on clock output |