36.5.13 SQI INTERRUPT ENABLE REGISTER
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTEN |
| Offset: | 0x11C |
| Reset: | 0x0000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DMAEIE | PKTCOMPIE | BDDONEIE | CONTHRIE | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CONEMPTYIE | CONFULLIE | RXTHRIE | RXFULLIE | RXEMPTYIE | TXTHRIE | TXFULLIE | TXEMPTYIE | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 11 – DMAEIE DMA Bus Error Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is disabled |
Bit 10 – PKTCOMPIE DMA Buffer Descriptor Packet Complete Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is disabled |
Bit 9 – BDDONEIE DMA Buffer Descriptor Done Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is disabled |
Bit 8 – CONTHRIE Control Buffer Threshold Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is disabled |
Bit 7 – CONEMPTYIE Control Buffer Empty Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is disabled |
Bit 6 – CONFULLIE Control Buffer Full Interrupt Enable bit
This bit enables an interrupt when the receive buffer is full.
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is disabled |
Bit 5 – RXTHRIE Receive Buffer Threshold Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is disabled |
Bit 4 – RXFULLIE Receive Buffer Full Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is disabled |
Bit 3 – RXEMPTYIE Receive Buffer Empty Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is disabled |
Bit 2 – TXTHRIE Transmit Threshold Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is disabled |
Bit 1 – TXFULLIE Transmit Buffer Full Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is disabled |
Bit 0 – TXEMPTYIE Transmit Buffer Empty Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is disabled |