37.15.13 PHY Control Register 48
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | PHY48 |
| Offset: | 0x1548 |
| Reset: | 0x00000004 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SESSENDTUNE[2:0] | VBUSCHRGE | FRCBSESSVAL | FRCASESSVAL | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 1 | 0 | 0 | |||
Bits 7:5 – SESSENDTUNE[2:0] Session End Reference Tuning
| Value | Description |
|---|---|
| 111 | 300 mV |
| 110 | 650 mV |
| 101 | 600 mV |
| 100 | 550 mV |
| 011 | 350 mV |
| 010 | 400 mV |
| 001 | 450 mV |
| 000 | 500 mV |
Bit 2 – VBUSCHRGE VBUS Charging/Discharging Bypass
| Value | Description |
|---|---|
| 1 | Default |
| 0 | - |
Bit 1 – FRCBSESSVAL Force B Session Valid
| Value | Description |
|---|---|
| 1 | - |
| 0 | Default |
Bit 0 – FRCASESSVAL Force A Session Valid
| Value | Description |
|---|---|
| 1 | - |
| 0 | Default |