37.15.11 PHY Control Register 28

Table 37-91. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: PHY28
Offset: 0x1528
Reset: 0x0000001B
Property: PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
 HSDRVCOMP[2:0]DISCONDET[3:0]HSDRIVST 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00011011 

Bits 7:5 – HSDRVCOMP[2:0] HS Driver Current Compensation

Sets the HS driver current compensation voltage reference.

ValueDescription
111362.5 mV
110375 mV
101387.5 mV
100450 mV
011437.5 mV
010425 mV
001412.5 mV
000400 mV

Bits 4:1 – DISCONDET[3:0] HOST Disconnect Detection

Sets the HOST disconnect detection trigger point.

ValueDescription
1111Reserved
1110612.5 mV
1101650 mV
1100Reserved
1011Reserved
101058705 mV
1001Reserved
1000600 mV
0111Reserved
0110537.5 mV
0101Reserved
0100550 mV
0011625 mV
0010562.5 mV
0001600 mV
0000575 mV

Bit 0 – HSDRIVST HS Transmit Driver Strength

Sets the HS transmit driver strength.

Settings include the lower bits (PHY24.6:7) and the upper bit (PHY28.0).

ValueDescription
111Strongest drive strength
000Weakest drive strength