36.5.22 SQI BUFFER DESCRIPTOR STATUS REGISTER
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | BDSTAT |
| Offset: | 0x144 |
| Reset: | 0x0000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| BDSTATE[3:0] | DMASTART | DMAACTV | |||||||
| Access | R | R | R | R | R | RO | |||
| Reset | 0 | 0 | 0 | x | x | x | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BDCON[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BDCON[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | x | |
Bits 21:18 – BDSTATE[3:0] DMA Buffer Descriptor Processor State Status bits <3:0>
These bits return the current state of the buffer descriptor processor:
| Value | Description |
|---|---|
| 5 | Fetched buffer descriptor is disabled |
| 4 | Descriptor is done |
| 3 | Data phase |
| 2 | Buffer descriptor is loading |
| 1 | Descriptor fetch request is pending |
| 0 | Idle |
Bit 17 – DMASTART DMA Buffer Descriptor Processor Start Status bit
| Value | Description |
|---|---|
| 1 | DMA has started |
| 0 | DMA has not started |
Bit 16 – DMAACTV DMA Buffer Descriptor Processor Active Status bit
| Value | Description |
|---|---|
| 1 | Buffer Descriptor Processor is active |
| 0 | Buffer Descriptor Processor is idle |
Bits 15:0 – BDCON[15:0] DMA Buffer Descriptor Control Word bits <15:0>
These bits contain the current buffer descriptor control word.