36.5.14 SQI INTERRUPT STATUS REGISTER
Note: The bits in the register are cleared by writing a '
1' to the
corresponding bit position| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTSTAT |
| Offset: | 0x120 |
| Reset: | 0x0000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DMAEIF | PKTCOMPIF | BDDONEIF | CONTHRIF | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CONEMPTYIF | CONFULLIF | RXTHRIF | RXFULLIF | RXEMPTYIF | TXTHRIF | TXFULLIF | TXEMPTYIF | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 |
Bit 11 – DMAEIF DMA Bus Error Interrupt Flag bit
| Value | Description |
|---|---|
| 1 | DMA bus error has occurred |
| 0 | DMA bus error has not occurred |
Bit 10 – PKTCOMPIF DMA Buffer Descriptor Processor Packet Completion Interrupt Flag bit
| Value | Description |
|---|---|
| 1 | DMA BD packet is complete |
| 0 | DMA BD packet is in progress |
Bit 9 – BDDONEIF DMA Buffer Descriptor Done Interrupt Flag bit
| Value | Description |
|---|---|
| 1 | DMA BD process is done |
| 0 | DMA BD process is in progress |
Bit 8 – CONTHRIF Control Buffer Threshold Interrupt Flag bit
| Value | Description |
|---|---|
| 1 | The control buffer has more than THRES words of space available |
| 0 | The control buffer has less than THRES words of space available |
Bit 7 – CONEMPTYIF Control Buffer Empty Interrupt Flag bit
| Value | Description |
|---|---|
| 1 | Control buffer is empty |
| 0 | Control buffer is not empty |
Bit 6 – CONFULLIF Control Buffer Full Interrupt Flag bit
| Value | Description |
|---|---|
| 1 | Control buffer is full |
| 0 | Control buffer is not full |
Bit 5 – RXTHRIF Receive Buffer Threshold Interrupt Flag bit
Note: In the case of Boot/xIP mode, the POR value of the receive buffer threshold is
zero. Therefore, this bit will be set to a '
1',immediately after a
POR until a read request on the System Bus bus is received.| Value | Description |
|---|---|
| 1 | Receive buffer has more than RXINTTHR words of space available |
| 0 | Receive buffer has less than RXINTTHR words of space available |
Bit 4 – RXFULLIF Receive Buffer Full Interrupt Flag bit
| Value | Description |
|---|---|
| 1 | Receive buffer is full |
| 0 | Receive buffer is not full |
Bit 3 – RXEMPTYIF Receive Buffer Empty Interrupt Flag bit
| Value | Description |
|---|---|
| 1 | Receive buffer is empty |
| 0 | Receive buffer is not empty |
Bit 2 – TXTHRIF Transmit Buffer Threshold Interrupt Flag bit
| Value | Description |
|---|---|
| 1 | Transmit buffer has more than TXINTTHR words of space available |
| 0 | Transmit buffer has less than TXINTTHR words of space available |
Bit 1 – TXFULLIF Transmit Buffer Full Interrupt Flag bit
| Value | Description |
|---|---|
| 1 | The transmit buffer is full |
| 0 | The transmit buffer is not full |
Bit 0 – TXEMPTYIF Transmit Buffer Empty Interrupt Flag bit
| Value | Description |
|---|---|
| 1 | The transmit buffer is empty |
| 0 | The transmit buffer has content |