36.5.29 SQI MEMORY STATUS CONTROL REGISTER
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | MEMSTAT |
| Offset: | 0x160 |
| Reset: | 0x0000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| STATPOS | STATTYPE[1:0] | STATBYTES[1:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| STATCMD[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| STATCMD[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 20 – STATPOS Status Bit Position in Flash bit
Indicates the BUSY bit position in the Flash Status register. This bit is added to support all Flash types (with BUSY bit at 0 and at 7).
| Value | Description |
|---|---|
| 1 | BUSY bit position is bit 7 in status register |
| 0 | BUSY bit position is bit 0 in status register |
Bits 19:18 – STATTYPE[1:0] Status Command Lane Mode bits <1:0>
| Value | Description |
|---|---|
| 11 | Reserved |
| 10 | Status command and read are executed in Quad Lane mode |
| 01 | Status command and read are executed in Dual Lane mode |
| 00 | Status command and read are executed in Single Lane mode |
Bits 17:16 – STATBYTES[1:0] Number of Status Bytes bits <1:0>
| Value | Description |
|---|---|
| 11 | Reserved |
| 10 | Status command is 2 bytes long |
| 01 | Status command is 1 byte long |
| 00 | Reserved |
Bits 15:0 – STATCMD[15:0] Status Command bits <15:0>
The status check command is written into these bits