36.5.1 Control A Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLA |
| Offset: | 0x000 |
| Reset: | 0x000 |
| Property: | PAC Write Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RUNSTDBY | SWRST | ||||||||
| Access | R/W | R/S/HC | |||||||
| Reset | 0 | 0 |
Bit 6 – RUNSTDBY Run in Standby
| Value | Description |
|---|---|
| 0 | Module is disabled in Standby Sleep mode |
| 1 | Module continues to run in Standby Sleep mode |
Bit 0 – SWRST Software Reset
Write a ‘1’ to this bit to reset the SFR registers including CTRLA.ENABLE. The bit stays high until reset completes. Setting this bit also sets the SYNCBUSY.SWRST to 1. SYNCBUSY.SWRST stays 1 until reset sequence completes.
Note:
- When the CTRLA.SWRST is written, the user should poll the SYNCB.SWRST bit to know when the reset operation is complete.
- During a SWRST, access to registers/bits without SWRST are disallowed until the SYNCBUSY.SWRST is cleared by the hardware.
| Value | Description |
|---|---|
| 0 | No reset in progress |
| 1 | Resetting |