PIC32CZ CA80/CA90 Family

36.5.17 SQI STATUS REGISTER 1

Table 36-17. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	STAT1
Offset:	0x12C
Reset:	0x0000
Property:	-


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
			TXBUFFREE[5:0]
Access			R	R	R	R	R	R
Reset			0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
			RXBUFCNT[5:0]
Access			R	R	R	R	R	R
Reset			0	0	0	0	0	0

Bits 21:16 – TXBUFFREE[5:0] Transmit buffer Available Word Space bits <5:0>

Bits 5:0 – RXBUFCNT[5:0] Number of words of read data in the buffer <5:0>

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