36.5.30 SQI XIP CONTROL REGISTER 3
Note: Some Flash devices require write
enable and sector unprotect commands before write/read operations and this register is
useful in working with those Flash types (xIP mode only)
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | XCON3 |
| Offset: | 0x164 |
| Reset: | 0x0000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| INIT1SCHECK | INIT1COUNT[1:0] | INIT1TYPE[1:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| INIT1CMD3[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| INIT1CMD2[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| INIT1CMD1[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 28 – INIT1SCHECK Flash Initialization 1 Command Status Check bit
| Value | Description |
|---|---|
| 1 | Check the status after executing the INIT1 commands |
| 0 | Do not check the status |
Bits 27:26 – INIT1COUNT[1:0] Flash Initialization 1 Command Count bits <1:0>
| Value | Description |
|---|---|
| 11 | INIT1CMD1, INIT1CMD2, and INIT1CMD3 are sent |
| 10 | INIT1CMD1 and INIT1CMD2 are sent, but INIT1CMD3 is still pending |
| 01 | INIT1CMD1 is sent, but INIT1CMD2 and INIT1CMD3 are still pending |
| 00 | No commands are sent |
Bits 25:24 – INIT1TYPE[1:0] Flash Initialization 1 Command Type bits <1:0>
| Value | Description |
|---|---|
| 11 | Reserved |
| 10 | INIT1 commands are sent in Quad Lane mode |
| 01 | INIT1 commands are sent in Dual Lane mode |
| 00 | INIT1 commands are sent in Single Lane mode |
Bits 24:16 – INIT1CMD3[8:0] Flash Initialization Command 3 bits <7:0>
Third command of the Flash initialization.
Bits 15:8 – INIT1CMD2[7:0] Flash Initialization Command 2 bits <7:0>
Second command of the Flash initialization.
Bits 7:0 – INIT1CMD1[7:0] Flash Initialization Command 1 bits <7:0>
First command of the Flash initialization.