47.5.13.4 16-BIT X 2 AUDIO PACK - AUDMOD=00, AUDFMT[2:0]=110(010), AUDWD_MODE[1:0]=10 OR 11, DATFMT_LR = 1 OR 0.
For I8S (I2S) standard mode, AM other formats mode 16-bit x 2 audio pack format, the configuration bits in SPIxCTRL_* must be set as follows: AUDMOD=00, AUDEN=1, FRMPOL=0, CPOL=1, CPHA=1, FRMSYPW=0100, FRMCNT=011, AUDFMT[2:0]=110, AUDWD_MODE[1:0]=10, FRMCOINC=0, DATFMT_LR=0. These values set SDO and LRC transitions to occur on the falling edge of SCK and sampling of SDI to occur on the rising edge of SCK. The following figure shows the format to store in memory.
As the data is serially sent in/out of the peripheral only the 16 bit sample is sent MSB first and the remaining lower bits not defined by the 16 bit sample (total of 32 bits in a quadlet/word) are don’t cares values but the bits are sent out to complete a 32-bit word per channel.
For an Example of 16-bit x 2 audio data flow see the following figure.
When the serial data is sent into the peripheral, the 32-bit word is reformed/packed to store in memory as shown in the following figures.
An I2S example for 16-bit x 2 audio packed format would be the same as the I8S above with the differences of 2 channels in-place of 8 channels and the frame would be 64 bit clocks instead of 256 bit clocks and the configuration is as follows: AUDMOD=00, AUDEN=1, FRMPOL=0, CPOL=1, CPHA=1, FRMSYPW=0001, FRMCNT=001, AUDFMT[2:0]=010, AUDWD_MODE[1:0]=10, FRMCOINC=0, DATFMT_LR=0.
