47.5.13.5 24, 20, 16-BIT MSB ALIGNED - OTHER FORMATS
I8S 24-bit MSB aligned format, the configuration bits in SPIxCTRL_* must be set as follows: AUDMOD=00, AUDEN=1, FRMPOL=0, CPOL=1, CPHA=1, FRMSYPW=0100, FRMCNT[2:0]=011, AUDFMT[2:0]=100, AUDWD_MODE[1:0]=10, FRMCOINC=0. These values set SDO and LRC transitions to occur on the falling edge of SCK and sampling of SDI to occur on the rising edge of SCK.
As the data is serially sent in/out of the peripheral only the 24bit sample with padding is sent MSB first (total of 32 bits in a quadlet/word). When the serial data is sent into the peripheral, the 32-bit word is stored in memory as shown in the following figures. When set to transmit (DISSDO = 0), this device drives the unused bit slots (preceding the audio data) with logic level 0. When set to receive (DISSDI = 0), this device ignores the unused bit slot I2S is supported as part of the legacy mode of operation and is not described here.
For an Example of 24-bit MSB Aligned audio data flow see the following figure.
