47.5.13.3 I8S (I2S)24-BIT X 4 AUDIO PACK - AUDMOD=00, AUDFMT[2:0]=110, AUDWD_MODE[1:0]=00
For I8S (I2S) standard mode, AM other format mode 24-bit x 4 audio pack format, the configuration bits in SPIxCTRL_* must be set as follows: AUDMOD=00, AUDEN=1, FRMPOL=0, CPOL=1, CPHA=1, FRMSYPW=0100, FRMCNT=011, AUDFMT[2:0]=110, AUDWD_MODE[1:0]=00, FRMCOINC=0. These values set SDO and LRC transitions to occur on the falling edge of SCK and sampling of SDI to occur on the rising edge of SCK.
As the data is serially sent in/out of the peripheral, only the 24 bit sample is captured or sent MSB first while the remaining lower bits of the 32 bit quadlet are don’t cares values. And the don’t care bits are also sent out to complete a 32-bit word per channel.
An Example of 24-bit x 4 audio data flow see the following figure. When the serial data is sent into the module, the 24-bit data sample are stored in a 32-bit word reformed/packed to store in memory.
An I2S example for 24-bit x 4 audio packed format would be the same as the I8S above with the differences of 2 channels in-place of 8 channels and the frame would be 64 bit clocks in stead of 256 bit clocks and the configuration is as follows:
AUDMOD=00, AUDEN=1, FRMPOL=0, CPOL=1, CPHA=1, FRMSYPW=0001, FRMCNT=001, AUD- FMT[2:0]=010, AUDWD_MODE[1:0]=00, FRMCO- INC=0, DATFMT_LR=0.
