47.5.13.7 I8S RIGHT JUSTIFIED MODE AUDMOD=10 AUDFMT = 001, 010,101, 110, 100

In Right Justified mode, the transmitter drives the audio data’s MSB on the SCK edge that is coincident with an LRC transition. The receiver samples the MSB on the next SCK edge. Right justified can be used for all I8S formats with AUDWD_MODE[1:0] 00, 01, 10 and AUDFMT[2:0] = 001, 010, 101, 110, 100 settings.

To configure for the I8S right justified standard convention, AM824 24-bit raw data, set the following bits in SPIxCTRL_* as follows: AUDMOD=10, AUDEN=1, FRMPOL=0, CPOL=1, CPHA = 1, FRMSYPW=0100, FRMCNT=011, AUDFMT[2:0] = 101, AUDWD_MODE[1:0] = 10, FRMCOINC=1. The following figure shows the waveform for this configuration.

An I2S example for AM824 24-bit raw data format would be the same as the I8S above with the differences of two channels in-place of 8 channels and the frame would be 64 bit clocks in stead of 256 bit clocks. For I2S AM824 24-bit use this configuration: AUD MOD=10 AUDEN=1, FRMPOL=0, CPOL=1, CPHA=1, FRMSYPW=0001, FRMCNT=001, AUDFMT[2:0]=001, AUDWD_MODE[1:0]=10, FRMCO INC=1.

Figure 47-36. I8S Right Justified Mode

To configure for the I8S right justified standard convention, AM824 24-bit raw with starting of a frame with the rising edge transition of LRC data, set the following bits in SPIxCTRL_* as follows: AUDMOD=10, AUDEN=1, FRMPOL=1, CPOL=0, CPHA=1, FRM- SYPW=0100, FRMCNT=011, AUDFMT[2:0]=101, AUDWD_MODE[1:0]=10, FRMCOINC=1.

The following figure shows the waveform for this configuration.

Figure 47-37. I8S Right Justified Mode with Rising Edge Transition LRC