42.6.3.3 Clocks Setup

The interface to the Advanced Peripheral Bus (APB) is clocked by the system’s Main Clock. The main clock, (GCLK0 or MCLK), can operate up to 300 MHz.

The ADC Core operates on a clock provided by the GCLK module, GCLK_ADC max 150Mhz. The register field GCLK.PCHCTRL41.GEN[2:0] is configured to select one of the GCLK’s clock generators. Clock generators are configured by the register GCLK.GENCTRLm , for m=0,1,…,8. This register selects the input clock for the generator and provides the clock divider to divide an input clock down to the clock output of GCLK Generator m . This clock is called the ADC Control Clock, or CTL_CLK in this chapter.

Each of the four ADC modules has a clock, TAD or ADC_CLOCK[n], n=0,1,2,3, that is divided down from the CTL_CLK. The divider for the respective ADCn is specified by CONFIG[n].CORCTRL.ADCDIV[6:0].