42.6.3.10 Initialization

The following steps are required to correctly configure the ADC for operation:

Step 1: Configure input pins for operation as analog input pins, ADCn_AINk .

Step 2: Configure a GCLK generator to provide the GCLK_ADC clock (PCHCTRLm index = 41).

Step 3: Configure ADC registers:

  • Copy factory-provided calibration values from Calibration Configuration Register FCCFG65 into CONFIG[n].CALCTRL for all the ADCn in use by the application
  • Configure CTRLA as needed but do not set CTRLA.ENABLE
  • Configure CTRLD, choosing the clock divider (CTLCKDIV) for the CTL_CLK clock based on the GCLK_ADC, Voltage Reference (VREFSEL), and Wake-up Delay Exponent (WKUPEXP)
  • (Optionally) Enable ADC interrupts for FIFO support using CTLINTENSET. Optionally enable the interrupts for VREFRDY and Core n ready. (Or these conditions can be monitored by watching CTLINTFLAG in a while(1) loop.) Enable interrupt vector 185 (ADC Global Interrupt) in the NVIC.
  • Enable ADC interrupts for each Module using the INTENSETn registers. Enable the corresponding NVIC interrupt vectors 186-189 (ADC Core Interrupts 0-3).
  • For each ADCn, configure its control register CONFIG[n].CORCTRL:
    • Set the clock divider, ADCDIV, for the ADC Module clock, CORE_CLK[n]
    • Set the sample count SAMC (ADCDIV and SAMC determine the ADC Module’s sample rate fs )
    • If ADC resolution other than 12 bits is desired, set it using SELRES
    • Other settings in CONFIG[n].CORCTRL as needed
  • Setup differential channels using CHNCFG3n.DIFFk = 1 for signals pairs k and k+1 (k even)
  • Select the input channels for each scan using CONFIG[n].CHNCFG2.CSSk = 1
  • Set the data format for each sample using CONFIG[n].CHNCFG2.FRACTk and CONFIG[n].CHNCFG3.SIGNk
  • Setup channel triggers
  • Optional: Setup up the Digital Filter and Digital Comparator associated with each of the four Modules

Step 4: Enable the ADC by setting CTRLA.ENABLE = 1.

Step 5: Wait until CTLINTFLAG.VREFRDY == 1, either using an ISR or polling in a while(1) loop. This signals that the chip’s analog environment is ready.

Step 6: Wait for CRRDYn to go high in CTLINTFLAG, indicating that the corresponding ADC Module is ready. This can be polled in a while(1) loop or trapped by the ISR attached to the ADC Global Interrupt