42.6.3.11 Channel Triggers

When two triggers arrive at the Access Arbiter at the same time the trigger associated with the input channel having the lower index k will be serviced. The second trigger will be queued for later service, provided it is not overwritten by a third trigger request. In that case, the third trigger will be lost and not serviced.

The trigger used for ADCn, Input Channel k, is specified by CONFIG[n].CHNCFG4|5.TRGSRCk[3:0]. (CONFIG[n].CHNCFG4 contains the trigger choices for k = 0,1,…,7. CONFIG[n].CHNCFG5 contains the trigger choices for k = 8,9,…,15. TRGSRCk for Sn ≤ k are not defined.)

The possible values for TRGSRCk are as follows:

= 0000: No Trigger (NOP)

= 0001: Global Software Trigger (CTRLB.GSWTRG)

= 0010: Global Level Software Trigger (CTRLB.LSWTRG)

= 0011: SCANTRG - Scan Trigger

= 0100: STRIG Synchronous Trigger

= 0101 - 1111: ADC Trigger Event User 0 – 10

Input channels with no triggers will not be serviced during the Module’s operation. For all trigger sources except the SCANTRG, setting the TRGSRCk will result in only input channel k being serviced by the Module. To collect a “scan” of input channels TRGSRCk must be set to SCANTRG and then SCANTRG is defined by CONFIG[n].CORCTRL.STRGSRC. All the input channels to be included in a scan started by SCANTRG must have CONFIG[n].CHNCFG2.CSSk set to one.

The SCANTRG source is selected by CONFIG[n].CORSTRL.STRGSRC:

= 0000: No trigger (NOP)

= 0001: Global Software trigger (CTRLB.GSWTRG)

= 0010: Level Software trigger (CTRLB.LSWTRG)

= 0011: Reserved

= 0100: Synchronous Trigger (STRIG)

= 0101 - 1111: EVSYS Event Generator 0 – 10

The Synchronous Trigger (STRIG) is driven by a counter at the ADC Control Clock (CTL_CLK) frequency and fires when the counter reaches the value defined by CTRLC.CNT[7:0]. To enable this clock set CTRLB.STRGEN to one.

ADC captures can be directly controlled from software by using the Global Software Trigger to start a single capture (when CTRLB.GSWTRG = 1) or by using the Global Level Software Trigger to start a burst of captures that will continue as long CTRLB.LSWTRG = 1 and stop when LSWTRG = 0.

Setting CTRLB.SWCNVEN = 1 allows two bits in CTRLB to control the Module specified by CTRLB.ADCORSEL and the input channel specified by CTRLB.ADCHSEL. For this to work all the other input channels for the Module specified by ADCORSEL must be disabled by setting TRGSRCk = 0, which can only be accomplished when the ADC is disabled. Sampling of the specified input channel starts when CTRLB.SAMP is set to one and stops when CTRLB.SAMP is reset to zero. Immediately after this start conversion by setting CTRLB.RQCNVRT to one.

The CTRLB register has a dedicated SYNCBUSY bit to allow the manipulation of these bits when the ADC is enabled. After writing to the CTRLB register the SYNCBUSY.CTRLB will go high. Wait until the bit goes low before writing to CTRLB again.

Trigger Rule 1: In order to ensure synchronizing every single pulse on GSWTRG, the GSWTRG pulses must be at least 4 ADC Control Clock periods apart, positive edge to positive edge (because the GSWTRG lasts only 1 single APB clock period by construction).

Trigger Rule 2: If a channel k is effectively included in scan n by setting CONFIG[n].CHNCFG4|5.TRGSRCk = 3 (SCANTRG) and CONFIG[n].CHNCFG2.CSSk = 1, then the user must ensure that no other triggers are generated for that channel using CTRLB.RQCNVRT or any digital filter. Otherwise the scan behavior is unpredictable.

Trigger Rule 3: To ensure synchronizing every single pulse on LSWTRG, the LSWTRG pulses must be at least 8 ADC Control Clock periods + 10 Main Clock clock periods positive edge to positive edge, and also at least 4 ADC control clock periods + 4 Main Clock periods negative edge to positive edge.

Trigger Rule 4: When using EVSYS for ADC triggers, only EVSYS asynchronous path, CHANNELn.PATH = 0x2, can be used to avoid ADC sampling and throughput timing inconsistencies.