42.6.3.4 Conversion Timing and Sampling Rate

If the period of CTL_CLK is TQ , then the period of the respective ADCn_CLK module clock, TAD , is given by:

TAD = 2·ADCDIV·TQ .

The minimum ADCn clock period is TAD = 2·TQ .

The maximum ADC throughput rate for ADC modules 1-3, with NBITS of resolution, is:

Provided CTRLB.SWCNVEN=0:

Maximum Throughput rate FTPR = [ 1/ [(CONFIG[n].CORCTRL.SAMC+2)TAD + (NBITS+1)TAD] ] / #Active ADCn Channels

For example:

(CONFIG[n].CORCTRL.SAMC = 0x1, 12-bit resolution and 2 AINx scan channels selected)

FTPR = [ 1/ (3TAD + 13TAD) ] / 2

= (1 / 16TAD) / 2

Important: The TAD clock must have the following characteristics:
  1. TAD <= 75 MHz.
  2. The highest value possible given the integer divisor relationship with the clock source, Examples are as follows:

Clock Source TAD CLOCK(min.):

300 MHz to 75 MHz

200 MHz to 50 MHz

150 MHz to 75 MHz

120 MHz to 60 MHz

72 MHz to 72 MHz