The Secure Distance Bounding mode uses a pseudo random scrambling scheme for the data symbols of
the RNRv and RNRp data for the prover and verifier operation. These modes require
setting up the Secure mode register A27 with the same data pattern in the verifier and
prover devices to enable the synchronous operation of the data scrambling.
Figure 3-8 illustrates the reordering process of the data
symbols (pulses) for the RNRp and RNRv data in the ATA8352 UWB device. Register A27
includes two data sections addressed by ID = 0 and ID =
1. Register A27 ID = 0 is preloaded with 32 or 64
indices (each 6-bit) in a random permutation order. Each index selects four data bits
with 8 or 16 symbols, that is, a total of 32 or 64 symbols for the bit mapping. Register
A27 ID = 1 is loaded with 80 bits for the initialization vector (IV)
and 80 bits for the key data (KEY) of the trivium cipher operation. The output patterns
of both blocks are finally XORed to form the 256 or 512 symbol pulse patterns for the 32
data bits. For a symbol-to-bit mapping of 8-to-1, a total of 32 indices are used, while
for a symbol-to-bit mapping of 16 to 1, a total of 64 indices are used.
Note: The ATA8350 UWB device does not allow
selecting between 32 or 64 indices as it is fixed at 64 indices.
Figure 3-8. Symbol Reordering
Process
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
