3.13 Supply Current Profile for Verifier and Prover

The following figure shows the supply current profile for a complete verifier operation, including power-up, initialization, Calibration Verifier Offset mode with prover response and power-down. The figure shows the analog signals for the supply voltage, VDD_CORE, and the current for the core domain, IDD_CORE, at 1.25V, and the supply domain, IDD_SUP, at 3.3V. At the bottom of the figure, the digital signals, N_RST, 1V2_ENA, SPI_CE and IRQ, display together with the controller state information. The complete sequence takes approximately 7.6 ms. The measurement was performed with the evaluation kit using an ATSAMC21 MCU with a 48 MHz clock and an SPI communication with an 8 MHz clock frequency. The supply current, IDD_SUP, includes the current for the VDD_IO domain and the current for a DC/DC converter to supply the domain, VDD_CORE (the DC/DC converter in this measurement was a MIC2203 device tuned to V_out = 1.25V), and assumes the typical efficiency for this DC/DC converter (approximately 85%).