3.9 UWB Device – Register Description

The UWB device has a set of registers that can be addressed through the SPI connection. Address the UWB device as an SPI client device, as the MCU device acts as SPI primary.

For example, A27_Secure mode in ATA8350 defined as:

A27.0 – Premutation
A27.1 – Trivium

Note: In comparison of both the ATA8350 and ATA8352 UWB devices, the SPI commands are explained more in detail in the ATA8352 UWB device.

The new SPI commands and the number of the bytes are highlighted in the Table 3-7.

Table 3-7. SPI Commands
SPI Command	Register Address	# of Bytes	Description
A0 – Bias1	0x00	5	Defines the bias setting for internal blocks during validation, and are not related to a frequency-setting change
A1 – Bias 2	0x01	5	Defines the bias setting for internal blocks during validation, and are needed during a frequency setting change
A2 – Enable	0x02	5	Enables various function blocks, and needs to be updated during setup and changes of operating modes
A3 – Crystal	0x03	6	Controls the behavior of the crystal oscillator
A4 – PLL	0x04	7⁽²⁾	Controls the operation of the PLL
A5 – FLL RX Write	0x05	6⁽²⁾	Defines the settings of the FLL for RX operation
A6 – FLL RX Read	0x06	4	Used to read the FLL frequency settings for the RX mode
A7 – RX FE	0x07	2	Includes settings for the RX front end
A8 – VGA	0x08	3	Includes settings for the VGA block
A9.0 – AGC Preamble⁽¹⁾	0x09	6⁽¹⁾	Includes settings for the AGC block during the preamble
A9.1 – AGC Postamble⁽¹⁾	0x09	6⁽¹⁾	Includes settings for the AGC block during the postamble
A10 – ADC	0x0A	3	Includes the settings for the ADC
A11– Demod	0x0B	3	Includes the settings for the demodulator (quadricorrelator and the phase-shifting network)
A12 – FLL TX Write	0x0C	7	Defines the settings of the FLL for TX operation
A13 – BFSK	0x0D	5⁽²⁾	Includes the settings of the BFSK block
A14 – TX PA	0x0E	6⁽²⁾	Includes the settings of the BFSK block
A15 – Pulse Shape1	0x0F	5	Includes the settings of the TX pulse shaper1
A16 – Pulse Shape2	0x10	5	Includes the settings of the TX pulse shaper2
A17 – FLL TX Read	0x11	4	Used to read the FLL frequency settings for the TX mode
A18 – Data	0x12	6,258,766	Used as a data register for different sections of data memory
A19 – Digital	0x13	4⁽²⁾	Used for controlling the device operating modes
A20.0 – ID⁽¹⁾	0x14	238⁽¹⁾	Used for debugging
A20.1 – ID⁽¹⁾	0x14	173⁽¹⁾	Used for debugging
A20.2 – ID⁽¹⁾	0x14	580⁽¹⁾	Used for debugging
A20.3 – ID⁽¹⁾	0x14	420⁽¹⁾	Used for debugging
A20.4 – ID⁽¹⁾	0x14	12⁽¹⁾	Used for debugging
A20.5 – ID⁽¹⁾	0x14	17⁽¹⁾	Used for debugging
A20.6 – ID⁽¹⁾	0x14	11⁽¹⁾	Used for debugging
A20.7 – ID⁽¹⁾	0x14	11⁽¹⁾	Used for debugging
A21 – GPO	0x15	5⁽²⁾	Used for debugging and validation purposes
A22 – Version	0x16	2	Contains the chip version
A23 – IRQ	0x17	2	Includes the interrupt mask and flag registers
A24 – SMR	0x18	45⁽²⁾	System Mode Register
A25 – ATB	0x19	3	Analog Test Bus (test only)
A26 – PAD	0x1A	7	PAD Configuration (test only)
A27.0 – Permutation⁽¹⁾	0x1B	50⁽¹⁾	Permutation of index table
A27.1 – Trivium⁽¹⁾	0x1B	22⁽¹⁾	Initialization vector and key for Trivium cipher operation
A28 – FLL CAL	0x1C	2	FLL calibration register

Note:

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