1.1.1.7 Bit Slip

The deserializer has a bit-slip feature for word alignment. In this mode, the CDR slips to the next bit from the deserializer. This feature helps with building word-alignment logic in the fabric. It is not used with the built-in 8b10b PCS core but is available for PMA only applications using fabric-based alignment. This feature adjusts the alignment of the deserialized word by 1-bit in either direction when the bit-slip feature is active, reducing the uncertainty by ensuring deterministic latency. This feature is supported by the transceiver configurator. The configurator enables this RX_SLIP input port. This port requests the transceiver CDR lane slip the parallel boundary by 1-bit.

In PMA mode applications, the RX_BIT_SLIP port is exposed on the block for the fabric to access. The RX_BIT_SLIP rising edge requests Rx data path slip relative to the RX_CLK by 1-bit (UI) using handshaking between RX_BIT_SLIP and RX_VAL. The handshake works as follows:

1. Fabric must wait for RX_VAL = 1. Then RX_BIT_SLIP may be asserted to initiate slip.
2. XCVR responds by lowering RX_VAL to 0.
3. Fabric then lowers RX_BIT_SLIP.
4. XCVR completes the slip and the RX_VAL is assigned to 1 synchronously with respect to RX_CLK rising edge.