1.1.2.2 Transmit PCS Divider

The PCS divider divides the bit-rate clock from the transmit PLL to a lower rate TX_CLK clock for use in the fabric. The PMA receives parallel data in the serializer up to 40 bits wide. This divider also sets the width of the parallel data received from the PCS to 8, 10, 16, 20, 32, 40, 64, and 80 bits. The specific ratio is a function of the parallel-to-serial or serial-to-parallel conversion in the PMA.