1.1.2.1 Serializer

The serializer provides the link between the high-speed interface and the transmit PCS by performing a parallel-to-serial conversion. Each lane has up to 40-bit data bus to the transmit PCS block and a separate post-divider for a divide by 1, 2, 4, 8, or 11. The post dividers are provided to divide the high-speed clock from the TxPLL to exactly what the serializer requires for the data rate. This allows sharing of a high-speed TxPLL by adjusting the local data rate within the transceiver lane. The glitch-free post-divider also allows for dynamic switching between dividers and data rates using the APB DRI.