1.3.1.4 8b10b System Registers

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There are specific registers used for configuring the 8b10b lane function options in the respective PolarFire Device Register Map or PolarFire SoC Register Map. Other fields are required to properly program the clocks, resets, XCVR, and lane overlay blocks and data path steering. Required system register field setting combinations required for enabling 8b10b lane usage.

Table 1-5. System Registers Affecting 8b10b Data Path
Register Page xls	Register Name	Field Name	Description	Required Value
pcslane	L8_R0	L8_TXENCSWAPSEL	Selects between 1000BASE-X/T and Fibre Channel octet-swapping modes.	Optional: 0=1000BASE-X/T, 1=Fibre Channel
	L8_R0	L8_GEARMODE[1:0]	Sets data path width of FWF interfaces.	Must be consistent with clock selections for txfwf_rclk and rxfwf_wclk.
	LOVR_R0	FAB_IFC_MODE[3:0]	Selects path through fabric and FWF overlay blocks.	Must be set to the 8b10b value (3'd4).
	LOVR_R0	PCSPMA_IFC_MODE[3:0]	Selects lane mode for driving data into the SerDes serializer.	Must be set to the 8b10b value (3'd4).
	LCLK_R0	LCLK_EPCS_RX_CLK_SEL [1:0]	Chooses which clock is sent to fabric on epcs_rx_clk port.	Usually this must be set to 2'd1 so that the frequency of the fabric is the same as the internal side of the FWF. However variations are possible if the use of the Rx FWF synchronous enable will be employed. See FWF description for further information.
pcslane	LCLK_R0	LCLK_EPCS_TX_CLK_SEL [1:0]	Chooses which clock is sent to fabric on epcs_tx_clk port.
		LCLK_PCS_RX_CLK_SEL [1:0]	Defines clock module's source for pcs_rx_clk.	Must be set to 2'd3 for all applications using 8B10B function.
		LCLK_PCS_TX_CLK_SEL [1:0]	Defines clock module's source for pcs_rx_clk.
		LCLK_RXFWF_WCLK_SEL [1:0]	Defines clock module's source for rxfwf_wclk.	Must be consistent with L8_GEARMODE setting.
		LCLK_TXFWF_RCLK_SEL [1:0]	Defines clock module's source for txfwf_rclk.	Must be consistent with L8_GEARMODE setting.
		LCLK_RXFWF_WCLK_PIPE	Defines whether Rx FWF is clocked by Tx side clocks or Rx side clocks.	Must be set to 1'd0 for 8B10B functionality.
	LCLK_R1	LCLK_ENA_8B10B_RX_CLK	Instructs clock module to drive 8B10B pcs_rx_clk.	Must be set to 1'd1 for 8B10B operation.
		LCLK_ENA_8B10B_RXFWF_WCLK	Instructs clock module to drive 8B10B rxfwf_wclk.
		LCLK_ENA_8B10B_TX_CLK	Instructs clock module to drive 8B10B pcs_tx_clk.
		LCLK_ENA_8B10B_TXFWF_WCLK	Instructs clock module to drive 8B10B txfwf_rclk.
pma_lane	DES_CLK_CTRL	DESMODE[2:0]	Selects parallel bus width of deserializer interface.	Must select the 40-bit wide bus mode for 8b10b functionality (3'd7).
	SER_CLK_CTRL	SERMODE[2:0]	Selects parallel bus width of serializer interface.
	DES_CDR_CTRL3	SLIP_DES_CDR_SEL	Selects source of CDR slip control.	Must be 1'd0 so that the fabric can control the symbol alignment.
	DES_CDR_CTRL3	SLIP_DES_CDR_EN	Optionally turns slip control off.	Must be set to 1'd1.

The following table lists the port names and description for the 8b10b mode of PCS module.

Table 1-6. 8b10b Port List
Port Name	Direction	Clock	Description
LANE#_CDR_REF_CLK_#/LANE#_CDR_REF_CLK_FAB	Input	—	Reference clock to lane CDR. Can be sourced from either an FPGA clock or from a XCVR_#[A,B,C]REFCLK_P/N pin.
LANE#_REF_CLK	Input	—	This port is exposed to user with Half-Duplex option. LANE#_REF_CLK must be connected by the user to a stable clock with same clock frequency as Recovered clock such as the local clock. Note: LANE#_REF_CLK can be provided by a separate PLL or CCC, however the LANE#_REF_CLK frequency must be within ± 300 ppm with respect to LANE#_RX_CLK_R.
LANE#_TX_PLL_REF_CLK_#	Input	—	Input clock from TX_PLL REF_CLK_TO_LANE output pin. Included in CLKS_FROM_TXPLL_# BIF (bus interface).
LANE#_TX_BIT_CLK_0	Input	—	Clock from BIT_CLK of the XCVR TxPLL. Included in CLKS_FROM_TXPLL_# BIF (bus interface).
LANE#_TX_PLL_LOCK_#	Input	—	Input lock status from TX_PLL LOCK output pin. Included in CLKS_FROM_TXPLL_# BIF (bus interface).
LANE#_TX_DISPFNC[N:0]¹	Input	TX_CLK_[R:G]	The TX_DISPFNC is a 2-bit encoded setting per octet where bit[1:0] is the lowest octet. The TX_DISPFNC port size is 4-bit, 8-bit, or 16-bit respective to 16-bit, 32-bit, or 64-bit PCS-Fabric interface widths. The TX_DISPFNC encoding is as follows for each octet per IEEE specification Clause 36 (802.3). The octet swap feature is designed such that the fabric marks the swap indicator on any octet of the interface. It is not necessary to align the K28.5 to octet 0 or octet 2. None - 2'b00 - Normally encode the octet with the encoder's current running disparity. Swap - 2'b01 - Search for tx_dispfnc = 1, swap next octet when running disparity prior to ordered set is ‘+’. ForcePlus - 2'b11 - Replace running disparity from encoder with ‘+’ when encoding associated octet. This tx_dispfnc occurs on any octet. ForceMinus - 2'b10 - Replace running disparity from encoder with ‘–’ when encoding associated octet. This tx_dispfnc occurs on any octet.
LANE#_8B10B_TX_K[N:0]²	Input	TX_CLK_[R:G]	Active-high signal indicating that TX_DATA contains  k-character information. This indicates that the input is a k-character byte, not a data byte.
LANE#_TX_DATA[N:0]	Input	TX_CLK_[R:G]	Encoded user data from the fabric. The send/receive order is low to high byte.
LANE#_PCS_ARST_N	Input	—	Asynchronous active-low reset for the PCS lane. This reset is responsible for the reset of the 8b10b logic and COMMA word aligner. The RX_SLIP is internally used to align the parallel word on the fabric interface, but does not reset the word aligner.
LANE#_PMA_ARST_N	Input	—	Asynchronous active-low reset for the PMA lane.
LANE#_RXD_N	Input	—	Transceiver receiver differential input.
LANE#_RXD_P	Input	—	Transceiver receiver differential input.
LANE#_8B10B_RX_K[N:0]²	Output	RX_CLK_[R:G]	Active-high output from the decoder to the receiver indicating that the received data is a K character. The order of character bits within an octet, in 8b10b mode, is least to most-significant bit as defined by 8b10b code notation. [0]: K decoded data on RX_DATA[7:0]. [1]: K decoded data on RX_DATA[15:8].
LANE#_RX_DISPARITY_ ERROR[N:0]²	Output	RX_CLK_[R:G]	Active-high output indicates when the received code group exists in the 8b10b decoding table but is not found in the proper column according to the current running disparity.
LANE#_RX_CODE_ VIOLATION[N:0]²	Output	RX_CLK_[R:G]	Active-high signal indicating that the decoder has detected an error in the received data.
LANE#_RX_DATA[N:0]³	Output	RX_CLK_[R:G]	Decoded user data to fabric. The send/receive data order is low to high byte meaning the octet order is least to most-significant. Data[7:0] = First octet  Data[15:8] = Second octet
LANE#_RX_VAL	Output	Synchronous	LANE#_RX_VAL indicates that the XCVR data path is initialized. The parallel bus of LANE#_RX_DATA[N:0] contains actual data recovered from the serial stream when LANE#_RX_VAL = 1. In 8b10b mode, the Rx PCS logic self-resets when the CDR is not locked. In this mode, LANE#_RX_VAL rises just after LANE#_RX_READY rises. Always pulse LANE#_PCS_ARST_N=0 using a clock independent from the LANE#_RX_CLK_R transceiver output. Asserting and holding LANE#_PCS_ARST_N=0 can prevent LANE#_PCS_RX_READY from rising and hold LANE#_RX_CLK_R at a static level. In 8b10b mode, the LANE#_RX_VAL is qualified when XCVR receiver calibration completes, included with the enhanced receiver management completion, and the CDR locks and the initial comma/word alignment occurs.
LANE#_RX_READY	Output	Asynchronous	Rises when the enhanced receiver management and CDR completes a fine lock detection to the incoming data transitions and the de-serializer is powered-up. If there is no incoming data to the CDR then the RX_READY is low. The primary purpose of this pin is to let the fabric know the CDR is locked to serial input data and is producing valid clocking. Note: In a loopback case where looping the local transmitter output to the receiver input, it is necessary to take the Tx out of reset to ensure valid serial transitions, allowing the Rx CDR to lock. If the user waits till Rx CDR locks before releasing Tx from reset, in such a case, the system deadlocks.
LANE#_RX_IDLE	Output	Asynchronous	Receive Electrical Idle (EI) detection flag. Flag is 1 when EI is valid. LANE#_Rx_IDLE peak detector logic is only valid for a limited minimum density of transitions on the Rx data and not to be used in applications above 5Gbps.
LANE#_TX_CLK_STABLE	Output	—	Transmit transceiver/PCS lane ready flag. This flag is 1 when the transmit PLL is locked to the reference clock.
LANE#_RX_CLK_[R:G]	Output	—	Global or regional receive clock to the fabric.⁴
LANE#_TX_CLK_[R:G]⁵	Output	—	Global or regional transmit clock to the fabric.⁴
LANE#_TXD_N	Output	—	Transceiver transmitter differential output.
LANE#_TXD_P	Output	—	Transceiver transmitter differential output.

Note:

N can be 1, 3, 7, and 15.
N can be 1, 3, and 7.
N can be 15, 31, and 63.
[R:G] naming is generated based on the use of regional or global resources that are selected with Libero. LANE# can be 0, 1, 2, and 3.
In PolarFire FPGA MPF500 devices, RT PolarFire RTPF500 devices, and PolarFire SoC FPGA devices, the TX_CLK_R and RX_CLK_R pins of XCVR lanes placed in the PCIESS (Q0) and GPSS1 (Q1) quads cannot drive I/Os.